Lines Matching +full:tcon +full:- +full:tv0
1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-h6.h"
42 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
75 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
92 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
107 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
129 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
147 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
162 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
177 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
192 .hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
222 .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
229 "iosc", "pll-cpux" };
233 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
236 "iosc", "pll-periph0" };
237 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
246 "psi-ahb1-ahb2",
247 "pll-periph0" };
266 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
267 "pll-ddr0", "pll-periph0-4x" };
274 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
281 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
284 static const char * const deinterlace_parents[] = { "pll-periph0",
285 "pll-periph1" };
294 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
298 static const char * const gpu_parents[] = { "pll-gpu" };
304 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
308 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
316 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
319 static const char * const ve_parents[] = { "pll-ve" };
326 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
336 static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2",
339 static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" };
346 static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2",
349 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
352 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
355 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
358 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
363 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
366 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
369 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
371 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
373 static const char * const dram_parents[] = { "pll-ddr0" };
386 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
388 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
390 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
392 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
394 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
396 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
398 static SUNXI_CCU_GATE(mbus_deinterlace_clk, "mbus-deinterlace", "mbus",
401 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
404 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
405 "pll-periph1", "pll-periph0-2x",
406 "pll-periph1-2x" };
421 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
423 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
424 "pll-periph1-2x" };
430 2, /* post-div */
438 2, /* post-div */
446 2, /* post-div */
449 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
450 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
451 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
453 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
454 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
455 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
456 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
458 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
459 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
460 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
461 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
463 static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0);
464 static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0);
480 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
481 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
483 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
485 static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
493 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
496 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_parents, 0x9c0,
503 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
505 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
507 static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x", "pll-audio-4x" };
560 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0);
561 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0);
562 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0);
563 static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0);
578 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
593 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
601 .hw.init = CLK_HW_INIT_PARENTS("audio-hub",
608 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
617 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
618 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
620 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
622 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
623 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0);
624 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0);
625 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0);
627 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
628 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
629 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
630 static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0);
631 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
632 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
635 static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M",
637 static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
639 static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref",
642 static SUNXI_CCU_M_WITH_GATE(pcie_maxi_clk, "pcie-maxi",
643 "pll-periph0", 0xab4,
648 static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8,
653 static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2",
656 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1",
657 "pll-video1-4x" };
664 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
666 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
686 .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
693 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
695 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
698 static const char * const tcon_lcd0_parents[] = { "pll-video0",
699 "pll-video0-4x",
700 "pll-video1" };
701 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
707 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
710 static const char * const tcon_tv0_parents[] = { "pll-video0",
711 "pll-video0-4x",
712 "pll-video1",
713 "pll-video1-4x" };
714 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
722 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
725 static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0);
727 static const char * const csi_top_parents[] = { "pll-video0", "pll-ve",
728 "pll-periph0" };
730 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top",
737 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0",
738 "pll-periph0", "pll-periph1" };
739 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk",
746 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0);
748 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
755 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
765 * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
766 * rates can be set exactly in conjunction with sigma-delta modulation.
768 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
771 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
774 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
781 static CLK_FIXED_FACTOR_HWS(pll_periph0_4x_clk, "pll-periph0-4x",
784 static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
791 static CLK_FIXED_FACTOR_HWS(pll_periph1_4x_clk, "pll-periph1-4x",
794 static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
798 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
801 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
1225 * See the comment before pll-video0 definition for the reason. in sun50i_h6_ccu_probe()
1246 * Force the post-divider of pll-audio to 12 and the output divider in sun50i_h6_ccu_probe()
1262 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc); in sun50i_h6_ccu_probe()
1274 { .compatible = "allwinner,sun50i-h6-ccu" },
1282 .name = "sun50i-h6-ccu",