Lines Matching +full:0 +full:x18c
29 { .index = 3, .shift = 0, .width = 5 },
44 .reg = 0x000,
49 0),
53 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
55 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
69 .reg = 0x010,
74 0),
86 0x11c, BIT(0), 0);
88 0x12c, BIT(0), 0);
90 0x13c, BIT(0), 0);
92 0x18c, BIT(0), 0);
94 0x19c, BIT(0), 0);
96 0x1bc, BIT(0), 0);
98 0x1cc, BIT(0), 0);
100 0x1ec, BIT(0), 0);
102 0x20c, BIT(0), CLK_IGNORE_UNUSED);
107 r_mod0_default_parents, 0x1c0,
108 0, 5, /* M */
112 0);
122 r_mod0_default_parents, 0x1e0,
123 0, 5, /* M */
127 0);
183 [RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
184 [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
185 [RST_R_APB1_PWM] = { 0x13c, BIT(16) },
186 [RST_R_APB2_UART] = { 0x18c, BIT(16) },
187 [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
188 [RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
189 [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
190 [RST_R_APB1_W1] = { 0x1ec, BIT(16) },
194 [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
195 [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
196 [RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
197 [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
229 reg = devm_platform_ioremap_resource(pdev, 0); in sun50i_h6_r_ccu_probe()