Lines Matching +full:0 +full:x65c
11 #define RCC_SECCFGR 0x0
12 #define RCC_MP_SREQSETR 0x100
13 #define RCC_MP_SREQCLRR 0x104
14 #define RCC_MP_APRSTCR 0x108
15 #define RCC_MP_APRSTSR 0x10c
16 #define RCC_PWRLPDLYCR 0x110
17 #define RCC_MP_GRSTCSETR 0x114
18 #define RCC_BR_RSTSCLRR 0x118
19 #define RCC_MP_RSTSSETR 0x11c
20 #define RCC_MP_RSTSCLRR 0x120
21 #define RCC_MP_IWDGFZSETR 0x124
22 #define RCC_MP_IWDGFZCLRR 0x128
23 #define RCC_MP_CIER 0x200
24 #define RCC_MP_CIFR 0x204
25 #define RCC_BDCR 0x400
26 #define RCC_RDLSICR 0x404
27 #define RCC_OCENSETR 0x420
28 #define RCC_OCENCLRR 0x424
29 #define RCC_OCRDYR 0x428
30 #define RCC_HSICFGR 0x440
31 #define RCC_CSICFGR 0x444
32 #define RCC_MCO1CFGR 0x460
33 #define RCC_MCO2CFGR 0x464
34 #define RCC_DBGCFGR 0x468
35 #define RCC_RCK12SELR 0x480
36 #define RCC_RCK3SELR 0x484
37 #define RCC_RCK4SELR 0x488
38 #define RCC_PLL1CR 0x4a0
39 #define RCC_PLL1CFGR1 0x4a4
40 #define RCC_PLL1CFGR2 0x4a8
41 #define RCC_PLL1FRACR 0x4ac
42 #define RCC_PLL1CSGR 0x4b0
43 #define RCC_PLL2CR 0x4d0
44 #define RCC_PLL2CFGR1 0x4d4
45 #define RCC_PLL2CFGR2 0x4d8
46 #define RCC_PLL2FRACR 0x4dc
47 #define RCC_PLL2CSGR 0x4e0
48 #define RCC_PLL3CR 0x500
49 #define RCC_PLL3CFGR1 0x504
50 #define RCC_PLL3CFGR2 0x508
51 #define RCC_PLL3FRACR 0x50c
52 #define RCC_PLL3CSGR 0x510
53 #define RCC_PLL4CR 0x520
54 #define RCC_PLL4CFGR1 0x524
55 #define RCC_PLL4CFGR2 0x528
56 #define RCC_PLL4FRACR 0x52c
57 #define RCC_PLL4CSGR 0x530
58 #define RCC_MPCKSELR 0x540
59 #define RCC_ASSCKSELR 0x544
60 #define RCC_MSSCKSELR 0x548
61 #define RCC_CPERCKSELR 0x54c
62 #define RCC_RTCDIVR 0x560
63 #define RCC_MPCKDIVR 0x564
64 #define RCC_AXIDIVR 0x568
65 #define RCC_MLAHBDIVR 0x56c
66 #define RCC_APB1DIVR 0x570
67 #define RCC_APB2DIVR 0x574
68 #define RCC_APB3DIVR 0x578
69 #define RCC_APB4DIVR 0x57c
70 #define RCC_APB5DIVR 0x580
71 #define RCC_APB6DIVR 0x584
72 #define RCC_TIMG1PRER 0x5a0
73 #define RCC_TIMG2PRER 0x5a4
74 #define RCC_TIMG3PRER 0x5a8
75 #define RCC_DDRITFCR 0x5c0
76 #define RCC_I2C12CKSELR 0x600
77 #define RCC_I2C345CKSELR 0x604
78 #define RCC_SPI2S1CKSELR 0x608
79 #define RCC_SPI2S23CKSELR 0x60c
80 #define RCC_SPI45CKSELR 0x610
81 #define RCC_UART12CKSELR 0x614
82 #define RCC_UART35CKSELR 0x618
83 #define RCC_UART4CKSELR 0x61c
84 #define RCC_UART6CKSELR 0x620
85 #define RCC_UART78CKSELR 0x624
86 #define RCC_LPTIM1CKSELR 0x628
87 #define RCC_LPTIM23CKSELR 0x62c
88 #define RCC_LPTIM45CKSELR 0x630
89 #define RCC_SAI1CKSELR 0x634
90 #define RCC_SAI2CKSELR 0x638
91 #define RCC_FDCANCKSELR 0x63c
92 #define RCC_SPDIFCKSELR 0x640
93 #define RCC_ADC12CKSELR 0x644
94 #define RCC_SDMMC12CKSELR 0x648
95 #define RCC_ETH12CKSELR 0x64c
96 #define RCC_USBCKSELR 0x650
97 #define RCC_QSPICKSELR 0x654
98 #define RCC_FMCCKSELR 0x658
99 #define RCC_RNG1CKSELR 0x65c
100 #define RCC_STGENCKSELR 0x660
101 #define RCC_DCMIPPCKSELR 0x664
102 #define RCC_SAESCKSELR 0x668
103 #define RCC_APB1RSTSETR 0x6a0
104 #define RCC_APB1RSTCLRR 0x6a4
105 #define RCC_APB2RSTSETR 0x6a8
106 #define RCC_APB2RSTCLRR 0x6ac
107 #define RCC_APB3RSTSETR 0x6b0
108 #define RCC_APB3RSTCLRR 0x6b4
109 #define RCC_APB4RSTSETR 0x6b8
110 #define RCC_APB4RSTCLRR 0x6bc
111 #define RCC_APB5RSTSETR 0x6c0
112 #define RCC_APB5RSTCLRR 0x6c4
113 #define RCC_APB6RSTSETR 0x6c8
114 #define RCC_APB6RSTCLRR 0x6cc
115 #define RCC_AHB2RSTSETR 0x6d0
116 #define RCC_AHB2RSTCLRR 0x6d4
117 #define RCC_AHB4RSTSETR 0x6e0
118 #define RCC_AHB4RSTCLRR 0x6e4
119 #define RCC_AHB5RSTSETR 0x6e8
120 #define RCC_AHB5RSTCLRR 0x6ec
121 #define RCC_AHB6RSTSETR 0x6f0
122 #define RCC_AHB6RSTCLRR 0x6f4
123 #define RCC_MP_APB1ENSETR 0x700
124 #define RCC_MP_APB1ENCLRR 0x704
125 #define RCC_MP_APB2ENSETR 0x708
126 #define RCC_MP_APB2ENCLRR 0x70c
127 #define RCC_MP_APB3ENSETR 0x710
128 #define RCC_MP_APB3ENCLRR 0x714
129 #define RCC_MP_S_APB3ENSETR 0x718
130 #define RCC_MP_S_APB3ENCLRR 0x71c
131 #define RCC_MP_NS_APB3ENSETR 0x720
132 #define RCC_MP_NS_APB3ENCLRR 0x724
133 #define RCC_MP_APB4ENSETR 0x728
134 #define RCC_MP_APB4ENCLRR 0x72c
135 #define RCC_MP_S_APB4ENSETR 0x730
136 #define RCC_MP_S_APB4ENCLRR 0x734
137 #define RCC_MP_NS_APB4ENSETR 0x738
138 #define RCC_MP_NS_APB4ENCLRR 0x73c
139 #define RCC_MP_APB5ENSETR 0x740
140 #define RCC_MP_APB5ENCLRR 0x744
141 #define RCC_MP_APB6ENSETR 0x748
142 #define RCC_MP_APB6ENCLRR 0x74c
143 #define RCC_MP_AHB2ENSETR 0x750
144 #define RCC_MP_AHB2ENCLRR 0x754
145 #define RCC_MP_AHB4ENSETR 0x760
146 #define RCC_MP_AHB4ENCLRR 0x764
147 #define RCC_MP_S_AHB4ENSETR 0x768
148 #define RCC_MP_S_AHB4ENCLRR 0x76c
149 #define RCC_MP_NS_AHB4ENSETR 0x770
150 #define RCC_MP_NS_AHB4ENCLRR 0x774
151 #define RCC_MP_AHB5ENSETR 0x778
152 #define RCC_MP_AHB5ENCLRR 0x77c
153 #define RCC_MP_AHB6ENSETR 0x780
154 #define RCC_MP_AHB6ENCLRR 0x784
155 #define RCC_MP_S_AHB6ENSETR 0x788
156 #define RCC_MP_S_AHB6ENCLRR 0x78c
157 #define RCC_MP_NS_AHB6ENSETR 0x790
158 #define RCC_MP_NS_AHB6ENCLRR 0x794
159 #define RCC_MP_APB1LPENSETR 0x800
160 #define RCC_MP_APB1LPENCLRR 0x804
161 #define RCC_MP_APB2LPENSETR 0x808
162 #define RCC_MP_APB2LPENCLRR 0x80c
163 #define RCC_MP_APB3LPENSETR 0x810
164 #define RCC_MP_APB3LPENCLRR 0x814
165 #define RCC_MP_S_APB3LPENSETR 0x818
166 #define RCC_MP_S_APB3LPENCLRR 0x81c
167 #define RCC_MP_NS_APB3LPENSETR 0x820
168 #define RCC_MP_NS_APB3LPENCLRR 0x824
169 #define RCC_MP_APB4LPENSETR 0x828
170 #define RCC_MP_APB4LPENCLRR 0x82c
171 #define RCC_MP_S_APB4LPENSETR 0x830
172 #define RCC_MP_S_APB4LPENCLRR 0x834
173 #define RCC_MP_NS_APB4LPENSETR 0x838
174 #define RCC_MP_NS_APB4LPENCLRR 0x83c
175 #define RCC_MP_APB5LPENSETR 0x840
176 #define RCC_MP_APB5LPENCLRR 0x844
177 #define RCC_MP_APB6LPENSETR 0x848
178 #define RCC_MP_APB6LPENCLRR 0x84c
179 #define RCC_MP_AHB2LPENSETR 0x850
180 #define RCC_MP_AHB2LPENCLRR 0x854
181 #define RCC_MP_AHB4LPENSETR 0x858
182 #define RCC_MP_AHB4LPENCLRR 0x85c
183 #define RCC_MP_S_AHB4LPENSETR 0x868
184 #define RCC_MP_S_AHB4LPENCLRR 0x86c
185 #define RCC_MP_NS_AHB4LPENSETR 0x870
186 #define RCC_MP_NS_AHB4LPENCLRR 0x874
187 #define RCC_MP_AHB5LPENSETR 0x878
188 #define RCC_MP_AHB5LPENCLRR 0x87c
189 #define RCC_MP_AHB6LPENSETR 0x880
190 #define RCC_MP_AHB6LPENCLRR 0x884
191 #define RCC_MP_S_AHB6LPENSETR 0x888
192 #define RCC_MP_S_AHB6LPENCLRR 0x88c
193 #define RCC_MP_NS_AHB6LPENSETR 0x890
194 #define RCC_MP_NS_AHB6LPENCLRR 0x894
195 #define RCC_MP_S_AXIMLPENSETR 0x898
196 #define RCC_MP_S_AXIMLPENCLRR 0x89c
197 #define RCC_MP_NS_AXIMLPENSETR 0x8a0
198 #define RCC_MP_NS_AXIMLPENCLRR 0x8a4
199 #define RCC_MP_MLAHBLPENSETR 0x8a8
200 #define RCC_MP_MLAHBLPENCLRR 0x8ac
201 #define RCC_APB3SECSR 0x8c0
202 #define RCC_APB4SECSR 0x8c4
203 #define RCC_APB5SECSR 0x8c8
204 #define RCC_APB6SECSR 0x8cc
205 #define RCC_AHB2SECSR 0x8d0
206 #define RCC_AHB4SECSR 0x8d4
207 #define RCC_AHB5SECSR 0x8d8
208 #define RCC_AHB6SECSR 0x8dc
209 #define RCC_VERR 0xff4
210 #define RCC_IDR 0xff8
211 #define RCC_SIDR 0xffc
214 #define RCC_SECCFGR_HSISEC 0
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
253 #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0)
254 #define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
273 #define RCC_MP_RSTSSETR_PORRSTF BIT(0)
289 #define RCC_MP_RSTSCLRR_PORRSTF BIT(0)
305 #define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0)
309 #define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0)
313 #define RCC_MP_CIER_LSIRDYIE BIT(0)
326 #define RCC_MP_CIFR_LSIRDYF BIT(0)
339 #define RCC_BDCR_LSEON BIT(0)
353 #define RCC_RDLSICR_LSION BIT(0)
363 #define RCC_OCENSETR_HSION BIT(0)
374 #define RCC_OCENCLRR_HSION BIT(0)
384 #define RCC_OCRDYR_HSIRDY BIT(0)
392 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
395 #define RCC_HSICFGR_HSIDIV_SHIFT 0
406 #define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0)
409 #define RCC_MCO1CFGR_MCO1SEL_SHIFT 0
413 #define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0)
416 #define RCC_MCO2CFGR_MCO2SEL_SHIFT 0
420 #define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0)
424 #define RCC_DBGCFGR_TRACEDIV_SHIFT 0
427 #define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0)
429 #define RCC_RCK12SELR_PLL12SRC_SHIFT 0
432 #define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0)
434 #define RCC_RCK3SELR_PLL3SRC_SHIFT 0
437 #define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0)
439 #define RCC_RCK4SELR_PLL4SRC_SHIFT 0
442 #define RCC_PLL1CR_PLLON BIT(0)
450 #define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0)
452 #define RCC_PLL1CFGR1_DIVN_SHIFT 0
456 #define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0)
459 #define RCC_PLL1CFGR2_DIVP_SHIFT 0
469 #define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0)
474 #define RCC_PLL1CSGR_MOD_PER_SHIFT 0
478 #define RCC_PLL2CR_PLLON BIT(0)
486 #define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0)
488 #define RCC_PLL2CFGR1_DIVN_SHIFT 0
492 #define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0)
495 #define RCC_PLL2CFGR2_DIVP_SHIFT 0
505 #define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0)
510 #define RCC_PLL2CSGR_MOD_PER_SHIFT 0
514 #define RCC_PLL3CR_PLLON BIT(0)
522 #define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0)
525 #define RCC_PLL3CFGR1_DIVN_SHIFT 0
530 #define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0)
533 #define RCC_PLL3CFGR2_DIVP_SHIFT 0
543 #define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0)
548 #define RCC_PLL3CSGR_MOD_PER_SHIFT 0
552 #define RCC_PLL4CR_PLLON BIT(0)
560 #define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0)
563 #define RCC_PLL4CFGR1_DIVN_SHIFT 0
568 #define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0)
571 #define RCC_PLL4CFGR2_DIVP_SHIFT 0
581 #define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0)
586 #define RCC_PLL4CSGR_MOD_PER_SHIFT 0
590 #define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)
592 #define RCC_MPCKSELR_MPUSRC_SHIFT 0
595 #define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0)
597 #define RCC_ASSCKSELR_AXISSRC_SHIFT 0
600 #define RCC_MSSCKSELR_MLAHBSSRC_MASK GENMASK(1, 0)
602 #define RCC_MSSCKSELR_MLAHBSSRC_SHIFT 0
605 #define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0)
606 #define RCC_CPERCKSELR_CKPERSRC_SHIFT 0
609 #define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0)
610 #define RCC_RTCDIVR_RTCDIV_SHIFT 0
613 #define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(3, 0)
615 #define RCC_MPCKDIVR_MPUDIV_SHIFT 0
618 #define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0)
620 #define RCC_AXIDIVR_AXIDIV_SHIFT 0
623 #define RCC_MLAHBDIVR_MLAHBDIV_MASK GENMASK(3, 0)
625 #define RCC_MLAHBDIVR_MLAHBDIV_SHIFT 0
628 #define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0)
630 #define RCC_APB1DIVR_APB1DIV_SHIFT 0
633 #define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0)
635 #define RCC_APB2DIVR_APB2DIV_SHIFT 0
638 #define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0)
640 #define RCC_APB3DIVR_APB3DIV_SHIFT 0
643 #define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0)
645 #define RCC_APB4DIVR_APB4DIV_SHIFT 0
648 #define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0)
650 #define RCC_APB5DIVR_APB5DIV_SHIFT 0
653 #define RCC_APB6DIVR_APB6DIV_MASK GENMASK(2, 0)
655 #define RCC_APB6DIVR_APB6DIV_SHIFT 0
658 #define RCC_TIMG1PRER_TIMG1PRE BIT(0)
662 #define RCC_TIMG2PRER_TIMG2PRE BIT(0)
666 #define RCC_TIMG3PRER_TIMG3PRE BIT(0)
670 #define RCC_DDRITFCR_DDRC1EN BIT(0)
697 #define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0)
698 #define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0
701 #define RCC_I2C345CKSELR_I2C3SRC_MASK GENMASK(2, 0)
704 #define RCC_I2C345CKSELR_I2C3SRC_SHIFT 0
709 #define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0)
710 #define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0
713 #define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0)
714 #define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0
717 #define RCC_SPI45CKSELR_SPI4SRC_MASK GENMASK(2, 0)
719 #define RCC_SPI45CKSELR_SPI4SRC_SHIFT 0
723 #define RCC_UART12CKSELR_UART1SRC_MASK GENMASK(2, 0)
725 #define RCC_UART12CKSELR_UART1SRC_SHIFT 0
729 #define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0)
730 #define RCC_UART35CKSELR_UART35SRC_SHIFT 0
733 #define RCC_UART4CKSELR_UART4SRC_MASK GENMASK(2, 0)
734 #define RCC_UART4CKSELR_UART4SRC_SHIFT 0
737 #define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0)
738 #define RCC_UART6CKSELR_UART6SRC_SHIFT 0
741 #define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0)
742 #define RCC_UART78CKSELR_UART78SRC_SHIFT 0
745 #define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0)
746 #define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0
749 #define RCC_LPTIM23CKSELR_LPTIM2SRC_MASK GENMASK(2, 0)
751 #define RCC_LPTIM23CKSELR_LPTIM2SRC_SHIFT 0
755 #define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0)
756 #define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0
759 #define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0)
760 #define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0
763 #define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0)
764 #define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0
767 #define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0)
768 #define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0
771 #define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0)
772 #define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0
775 #define RCC_ADC12CKSELR_ADC1SRC_MASK GENMASK(1, 0)
777 #define RCC_ADC12CKSELR_ADC1SRC_SHIFT 0
781 #define RCC_SDMMC12CKSELR_SDMMC1SRC_MASK GENMASK(2, 0)
783 #define RCC_SDMMC12CKSELR_SDMMC1SRC_SHIFT 0
787 #define RCC_ETH12CKSELR_ETH1SRC_MASK GENMASK(1, 0)
791 #define RCC_ETH12CKSELR_ETH1SRC_SHIFT 0
797 #define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0)
799 #define RCC_USBCKSELR_USBPHYSRC_SHIFT 0
802 #define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0)
803 #define RCC_QSPICKSELR_QSPISRC_SHIFT 0
806 #define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0)
807 #define RCC_FMCCKSELR_FMCSRC_SHIFT 0
810 #define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0)
811 #define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0
814 #define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0)
815 #define RCC_STGENCKSELR_STGENSRC_SHIFT 0
818 #define RCC_DCMIPPCKSELR_DCMIPPSRC_MASK GENMASK(1, 0)
819 #define RCC_DCMIPPCKSELR_DCMIPPSRC_SHIFT 0
822 #define RCC_SAESCKSELR_SAESSRC_MASK GENMASK(1, 0)
823 #define RCC_SAESCKSELR_SAESSRC_SHIFT 0
826 #define RCC_APB1RSTSETR_TIM2RST BIT(0)
845 #define RCC_APB1RSTCLRR_TIM2RST BIT(0)
864 #define RCC_APB2RSTSETR_TIM1RST BIT(0)
874 #define RCC_APB2RSTCLRR_TIM1RST BIT(0)
884 #define RCC_APB3RSTSETR_LPTIM2RST BIT(0)
894 #define RCC_APB3RSTCLRR_LPTIM2RST BIT(0)
904 #define RCC_APB4RSTSETR_LTDCRST BIT(0)
910 #define RCC_APB4RSTCLRR_LTDCRST BIT(0)
922 #define RCC_APB6RSTSETR_USART1RST BIT(0)
937 #define RCC_APB6RSTCLRR_USART1RST BIT(0)
952 #define RCC_AHB2RSTSETR_DMA1RST BIT(0)
962 #define RCC_AHB2RSTCLRR_DMA1RST BIT(0)
972 #define RCC_AHB4RSTSETR_GPIOARST BIT(0)
984 #define RCC_AHB4RSTCLRR_GPIOARST BIT(0)
1012 #define RCC_AHB6RSTSETR_MDMARST BIT(0)
1024 #define RCC_AHB6RSTCLRR_MDMARST BIT(0)
1036 #define RCC_MP_APB1ENSETR_TIM2EN BIT(0)
1055 #define RCC_MP_APB1ENCLRR_TIM2EN BIT(0)
1074 #define RCC_MP_APB2ENSETR_TIM1EN BIT(0)
1085 #define RCC_MP_APB2ENCLRR_TIM1EN BIT(0)
1096 #define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0)
1106 #define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0)
1116 #define RCC_MP_S_APB3ENSETR_SYSCFGEN BIT(0)
1119 #define RCC_MP_S_APB3ENCLRR_SYSCFGEN BIT(0)
1122 #define RCC_MP_NS_APB3ENSETR_SYSCFGEN BIT(0)
1125 #define RCC_MP_NS_APB3ENCLRR_SYSCFGEN BIT(0)
1142 #define RCC_MP_S_APB4ENSETR_LTDCEN BIT(0)
1145 #define RCC_MP_S_APB4ENCLRR_LTDCEN BIT(0)
1148 #define RCC_MP_NS_APB4ENSETR_LTDCEN BIT(0)
1151 #define RCC_MP_NS_APB4ENCLRR_LTDCEN BIT(0)
1170 #define RCC_MP_APB6ENSETR_USART1EN BIT(0)
1185 #define RCC_MP_APB6ENCLRR_USART1EN BIT(0)
1200 #define RCC_MP_AHB2ENSETR_DMA1EN BIT(0)
1210 #define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0)
1226 #define RCC_MP_S_AHB4ENSETR_GPIOAEN BIT(0)
1237 #define RCC_MP_S_AHB4ENCLRR_GPIOAEN BIT(0)
1248 #define RCC_MP_NS_AHB4ENSETR_GPIOAEN BIT(0)
1259 #define RCC_MP_NS_AHB4ENCLRR_GPIOAEN BIT(0)
1322 #define RCC_MP_S_AHB6ENSETR_MDMAEN BIT(0)
1325 #define RCC_MP_S_AHB6ENCLRR_MDMAEN BIT(0)
1328 #define RCC_MP_NS_AHB6ENSETR_MDMAEN BIT(0)
1331 #define RCC_MP_NS_AHB6ENCLRR_MDMAEN BIT(0)
1334 #define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0)
1353 #define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0)
1372 #define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0)
1383 #define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0)
1394 #define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0)
1403 #define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0)
1412 #define RCC_MP_S_APB3LPENSETR_SYSCFGLPEN BIT(0)
1415 #define RCC_MP_S_APB3LPENCLRR_SYSCFGLPEN BIT(0)
1418 #define RCC_MP_NS_APB3LPENSETR_SYSCFGLPEN BIT(0)
1421 #define RCC_MP_NS_APB3LPENCLRR_SYSCFGLPEN BIT(0)
1440 #define RCC_MP_S_APB4LPENSETR_LTDCLPEN BIT(0)
1443 #define RCC_MP_S_APB4LPENCLRR_LTDCLPEN BIT(0)
1446 #define RCC_MP_NS_APB4LPENSETR_LTDCLPEN BIT(0)
1449 #define RCC_MP_NS_APB4LPENCLRR_LTDCLPEN BIT(0)
1470 #define RCC_MP_APB6LPENSETR_USART1LPEN BIT(0)
1485 #define RCC_MP_APB6LPENCLRR_USART1LPEN BIT(0)
1500 #define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0)
1510 #define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0)
1526 #define RCC_MP_S_AHB4LPENSETR_GPIOALPEN BIT(0)
1537 #define RCC_MP_S_AHB4LPENCLRR_GPIOALPEN BIT(0)
1548 #define RCC_MP_NS_AHB4LPENSETR_GPIOALPEN BIT(0)
1559 #define RCC_MP_NS_AHB4LPENCLRR_GPIOALPEN BIT(0)
1624 #define RCC_MP_S_AHB6LPENSETR_MDMALPEN BIT(0)
1627 #define RCC_MP_S_AHB6LPENCLRR_MDMALPEN BIT(0)
1630 #define RCC_MP_NS_AHB6LPENSETR_MDMALPEN BIT(0)
1633 #define RCC_MP_NS_AHB6LPENCLRR_MDMALPEN BIT(0)
1636 #define RCC_MP_S_AXIMLPENSETR_SYSRAMLPEN BIT(0)
1639 #define RCC_MP_S_AXIMLPENCLRR_SYSRAMLPEN BIT(0)
1642 #define RCC_MP_NS_AXIMLPENSETR_SYSRAMLPEN BIT(0)
1645 #define RCC_MP_NS_AXIMLPENCLRR_SYSRAMLPEN BIT(0)
1648 #define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0)
1653 #define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0)
1658 #define RCC_APB3SECSR_LPTIM2SECF 0
1677 #define RCC_APB6SECSR_USART1SECF 0
1734 #define RCC_VERR_MINREV_MASK GENMASK(3, 0)
1736 #define RCC_VERR_MINREV_SHIFT 0
1740 #define RCC_IDR_ID_MASK GENMASK(31, 0)
1741 #define RCC_IDR_ID_SHIFT 0
1744 #define RCC_SIDR_SID_MASK GENMASK(31, 0)
1745 #define RCC_SIDR_SID_SHIFT 0