25 #define STM32MP1_RESET_ID_MASK GENMASK(15, 0)
29 #define RCC_OCENSETR		0x0C
30 #define RCC_HSICFGR		0x18
31 #define RCC_RDLSICR		0x144
32 #define RCC_PLL1CR		0x80
33 #define RCC_PLL1CFGR1		0x84
34 #define RCC_PLL1CFGR2		0x88
35 #define RCC_PLL2CR		0x94
36 #define RCC_PLL2CFGR1		0x98
37 #define RCC_PLL2CFGR2		0x9C
38 #define RCC_PLL3CR		0x880
39 #define RCC_PLL3CFGR1		0x884
40 #define RCC_PLL3CFGR2		0x888
41 #define RCC_PLL4CR		0x894
42 #define RCC_PLL4CFGR1		0x898
43 #define RCC_PLL4CFGR2		0x89C
44 #define RCC_APB1ENSETR		0xA00
45 #define RCC_APB2ENSETR		0xA08
46 #define RCC_APB3ENSETR		0xA10
47 #define RCC_APB4ENSETR		0x200
48 #define RCC_APB5ENSETR		0x208
49 #define RCC_AHB2ENSETR		0xA18
50 #define RCC_AHB3ENSETR		0xA20
51 #define RCC_AHB4ENSETR		0xA28
52 #define RCC_AHB5ENSETR		0x210
53 #define RCC_AHB6ENSETR		0x218
54 #define RCC_AHB6LPENSETR	0x318
55 #define RCC_RCK12SELR		0x28
56 #define RCC_RCK3SELR		0x820
57 #define RCC_RCK4SELR		0x824
58 #define RCC_MPCKSELR		0x20
59 #define RCC_ASSCKSELR		0x24
60 #define RCC_MSSCKSELR		0x48
61 #define RCC_SPI6CKSELR		0xC4
62 #define RCC_SDMMC12CKSELR	0x8F4
63 #define RCC_SDMMC3CKSELR	0x8F8
64 #define RCC_FMCCKSELR		0x904
65 #define RCC_I2C46CKSELR		0xC0
66 #define RCC_I2C12CKSELR		0x8C0
67 #define RCC_I2C35CKSELR		0x8C4
68 #define RCC_UART1CKSELR		0xC8
69 #define RCC_QSPICKSELR		0x900
70 #define RCC_ETHCKSELR		0x8FC
71 #define RCC_RNG1CKSELR		0xCC
72 #define RCC_RNG2CKSELR		0x920
73 #define RCC_GPUCKSELR		0x938
74 #define RCC_USBCKSELR		0x91C
75 #define RCC_STGENCKSELR		0xD4
76 #define RCC_SPDIFCKSELR		0x914
77 #define RCC_SPI2S1CKSELR	0x8D8
78 #define RCC_SPI2S23CKSELR	0x8DC
79 #define RCC_SPI2S45CKSELR	0x8E0
80 #define RCC_CECCKSELR		0x918
81 #define RCC_LPTIM1CKSELR	0x934
82 #define RCC_LPTIM23CKSELR	0x930
83 #define RCC_LPTIM45CKSELR	0x92C
84 #define RCC_UART24CKSELR	0x8E8
85 #define RCC_UART35CKSELR	0x8EC
86 #define RCC_UART6CKSELR		0x8E4
87 #define RCC_UART78CKSELR	0x8F0
88 #define RCC_FDCANCKSELR		0x90C
89 #define RCC_SAI1CKSELR		0x8C8
90 #define RCC_SAI2CKSELR		0x8CC
91 #define RCC_SAI3CKSELR		0x8D0
92 #define RCC_SAI4CKSELR		0x8D4
93 #define RCC_ADCCKSELR		0x928
94 #define RCC_MPCKDIVR		0x2C
95 #define RCC_DSICKSELR		0x924
96 #define RCC_CPERCKSELR		0xD0
97 #define RCC_MCO1CFGR		0x800
98 #define RCC_MCO2CFGR		0x804
99 #define RCC_BDCR		0x140
100 #define RCC_AXIDIVR		0x30
101 #define RCC_MCUDIVR		0x830
102 #define RCC_APB1DIVR		0x834
103 #define RCC_APB2DIVR		0x838
104 #define RCC_APB3DIVR		0x83C
105 #define RCC_APB4DIVR		0x3C
106 #define RCC_APB5DIVR		0x40
107 #define RCC_TIMG1PRER		0x828
108 #define RCC_TIMG2PRER		0x82C
109 #define RCC_RTCDIVR		0x44
110 #define RCC_DBGCFGR		0x80C
112 #define RCC_CLR	0x4
275 	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
277 	{ 0 },
281 	{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
285 	{ 0 },
289 	{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
291 	{ 0 },
295 	{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
297 	{ 0 },
338 #define NO_ID ~0
463 	return 0;  in mp1_gate_clk_enable()
469 	unsigned long flags = 0;  in mp1_gate_clk_disable()
691 	return  0;  in mp1_mgate_clk_enable()
701 	if (clk_mgate->mgate->flag == 0)  in mp1_mgate_clk_disable()
732 	for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)  in clk_mmux_set_parent()
736 	return 0;  in clk_mmux_set_parent()
756 #define PLL_ON		BIT(0)
758 #define DIVN_MASK	0x1FF
759 #define DIVM_MASK	0x3F
761 #define DIVN_SHIFT	0
762 #define FRAC_OFFSET	0xC
763 #define FRAC_MASK	0x1FFF
766 #define PLL_MUX_SHIFT	0
782 	unsigned long flags = 0;  in pll_enable()
784 	int bit_status = 0;  in pll_enable()
818 	unsigned long flags = 0;  in pll_disable()
832 	u32 reg, frac = 0;  in pll_frac_val()
847 	u64 rate, rate_frac = 0;  in pll_recalc_rate()
869 	unsigned long flags = 0;  in pll_is_enabled()
951 #define APB_DIV_MASK 0x07
952 #define TIM_PRE_MASK 0x01
959 	unsigned int mult = 0;  in __bestmult()
985 	unsigned long flags = 0;  in timer_ker_set_rate()
987 	int ret = 0;  in timer_ker_set_rate()
995 		writel_relaxed(0, tim_ker->timpre);  in timer_ker_set_rate()
1098 	return 0;  in clk_divider_rtc_determine_rate()
1263 			   _offset_set, _bit_idx, 0)
1536 	K_GATE(G_MDIO,		RCC_APB1ENSETR, 31, 0),
1537 	K_MGATE(G_DAC12,	RCC_APB1ENSETR, 29, 0),
1538 	K_MGATE(G_CEC,		RCC_APB1ENSETR, 27, 0),
1539 	K_MGATE(G_SPDIF,	RCC_APB1ENSETR, 26, 0),
1540 	K_MGATE(G_I2C5,		RCC_APB1ENSETR, 24, 0),
1541 	K_MGATE(G_I2C3,		RCC_APB1ENSETR, 23, 0),
1542 	K_MGATE(G_I2C2,		RCC_APB1ENSETR, 22, 0),
1543 	K_MGATE(G_I2C1,		RCC_APB1ENSETR, 21, 0),
1544 	K_MGATE(G_UART8,	RCC_APB1ENSETR, 19, 0),
1545 	K_MGATE(G_UART7,	RCC_APB1ENSETR, 18, 0),
1546 	K_MGATE(G_UART5,	RCC_APB1ENSETR, 17, 0),
1547 	K_MGATE(G_UART4,	RCC_APB1ENSETR, 16, 0),
1548 	K_MGATE(G_USART3,	RCC_APB1ENSETR, 15, 0),
1549 	K_MGATE(G_USART2,	RCC_APB1ENSETR, 14, 0),
1550 	K_MGATE(G_SPI3,		RCC_APB1ENSETR, 12, 0),
1551 	K_MGATE(G_SPI2,		RCC_APB1ENSETR, 11, 0),
1552 	K_MGATE(G_LPTIM1,	RCC_APB1ENSETR, 9, 0),
1553 	K_GATE(G_TIM14,		RCC_APB1ENSETR, 8, 0),
1554 	K_GATE(G_TIM13,		RCC_APB1ENSETR, 7, 0),
1555 	K_GATE(G_TIM12,		RCC_APB1ENSETR, 6, 0),
1556 	K_GATE(G_TIM7,		RCC_APB1ENSETR, 5, 0),
1557 	K_GATE(G_TIM6,		RCC_APB1ENSETR, 4, 0),
1558 	K_GATE(G_TIM5,		RCC_APB1ENSETR, 3, 0),
1559 	K_GATE(G_TIM4,		RCC_APB1ENSETR, 2, 0),
1560 	K_GATE(G_TIM3,		RCC_APB1ENSETR, 1, 0),
1561 	K_GATE(G_TIM2,		RCC_APB1ENSETR, 0, 0),
1563 	K_MGATE(G_FDCAN,	RCC_APB2ENSETR, 24, 0),
1564 	K_GATE(G_ADFSDM,	RCC_APB2ENSETR, 21, 0),
1565 	K_GATE(G_DFSDM,		RCC_APB2ENSETR, 20, 0),
1566 	K_MGATE(G_SAI3,		RCC_APB2ENSETR, 18, 0),
1567 	K_MGATE(G_SAI2,		RCC_APB2ENSETR, 17, 0),
1568 	K_MGATE(G_SAI1,		RCC_APB2ENSETR, 16, 0),
1569 	K_MGATE(G_USART6,	RCC_APB2ENSETR, 13, 0),
1570 	K_MGATE(G_SPI5,		RCC_APB2ENSETR, 10, 0),
1571 	K_MGATE(G_SPI4,		RCC_APB2ENSETR, 9, 0),
1572 	K_MGATE(G_SPI1,		RCC_APB2ENSETR, 8, 0),
1573 	K_GATE(G_TIM17,		RCC_APB2ENSETR, 4, 0),
1574 	K_GATE(G_TIM16,		RCC_APB2ENSETR, 3, 0),
1575 	K_GATE(G_TIM15,		RCC_APB2ENSETR, 2, 0),
1576 	K_GATE(G_TIM8,		RCC_APB2ENSETR, 1, 0),
1577 	K_GATE(G_TIM1,		RCC_APB2ENSETR, 0, 0),
1579 	K_GATE(G_HDP,		RCC_APB3ENSETR, 20, 0),
1580 	K_GATE(G_PMBCTRL,	RCC_APB3ENSETR, 17, 0),
1581 	K_GATE(G_TMPSENS,	RCC_APB3ENSETR, 16, 0),
1582 	K_GATE(G_VREF,		RCC_APB3ENSETR, 13, 0),
1583 	K_GATE(G_SYSCFG,	RCC_APB3ENSETR, 11, 0),
1584 	K_MGATE(G_SAI4,		RCC_APB3ENSETR, 8, 0),
1585 	K_MGATE(G_LPTIM5,	RCC_APB3ENSETR, 3, 0),
1586 	K_MGATE(G_LPTIM4,	RCC_APB3ENSETR, 2, 0),
1587 	K_MGATE(G_LPTIM3,	RCC_APB3ENSETR, 1, 0),
1588 	K_MGATE(G_LPTIM2,	RCC_APB3ENSETR, 0, 0),
1590 	K_GATE(G_STGENRO,	RCC_APB4ENSETR, 20, 0),
1591 	K_MGATE(G_USBPHY,	RCC_APB4ENSETR, 16, 0),
1592 	K_GATE(G_IWDG2,		RCC_APB4ENSETR, 15, 0),
1593 	K_GATE(G_DDRPERFM,	RCC_APB4ENSETR, 8, 0),
1594 	K_MGATE(G_DSI,		RCC_APB4ENSETR, 4, 0),
1595 	K_MGATE(G_LTDC,		RCC_APB4ENSETR, 0, 0),
1597 	K_GATE(G_STGEN,		RCC_APB5ENSETR, 20, 0),
1598 	K_GATE(G_BSEC,		RCC_APB5ENSETR, 16, 0),
1599 	K_GATE(G_IWDG1,		RCC_APB5ENSETR, 15, 0),
1600 	K_GATE(G_TZPC,		RCC_APB5ENSETR, 13, 0),
1601 	K_GATE(G_TZC2,		RCC_APB5ENSETR, 12, 0),
1602 	K_GATE(G_TZC1,		RCC_APB5ENSETR, 11, 0),
1603 	K_GATE(G_RTCAPB,	RCC_APB5ENSETR, 8, 0),
1604 	K_MGATE(G_USART1,	RCC_APB5ENSETR, 4, 0),
1605 	K_MGATE(G_I2C6,		RCC_APB5ENSETR, 3, 0),
1606 	K_MGATE(G_I2C4,		RCC_APB5ENSETR, 2, 0),
1607 	K_MGATE(G_SPI6,		RCC_APB5ENSETR, 0, 0),
1609 	K_MGATE(G_SDMMC3,	RCC_AHB2ENSETR, 16, 0),
1610 	K_MGATE(G_USBO,		RCC_AHB2ENSETR, 8, 0),
1611 	K_MGATE(G_ADC12,	RCC_AHB2ENSETR, 5, 0),
1612 	K_GATE(G_DMAMUX,	RCC_AHB2ENSETR, 2, 0),
1613 	K_GATE(G_DMA2,		RCC_AHB2ENSETR, 1, 0),
1614 	K_GATE(G_DMA1,		RCC_AHB2ENSETR, 0, 0),
1616 	K_GATE(G_IPCC,		RCC_AHB3ENSETR, 12, 0),
1617 	K_GATE(G_HSEM,		RCC_AHB3ENSETR, 11, 0),
1618 	K_GATE(G_CRC2,		RCC_AHB3ENSETR, 7, 0),
1619 	K_MGATE(G_RNG2,		RCC_AHB3ENSETR, 6, 0),
1620 	K_GATE(G_HASH2,		RCC_AHB3ENSETR, 5, 0),
1621 	K_GATE(G_CRYP2,		RCC_AHB3ENSETR, 4, 0),
1622 	K_GATE(G_DCMI,		RCC_AHB3ENSETR, 0, 0),
1624 	K_GATE(G_GPIOK,		RCC_AHB4ENSETR, 10, 0),
1625 	K_GATE(G_GPIOJ,		RCC_AHB4ENSETR, 9, 0),
1626 	K_GATE(G_GPIOI,		RCC_AHB4ENSETR, 8, 0),
1627 	K_GATE(G_GPIOH,		RCC_AHB4ENSETR, 7, 0),
1628 	K_GATE(G_GPIOG,		RCC_AHB4ENSETR, 6, 0),
1629 	K_GATE(G_GPIOF,		RCC_AHB4ENSETR, 5, 0),
1630 	K_GATE(G_GPIOE,		RCC_AHB4ENSETR, 4, 0),
1631 	K_GATE(G_GPIOD,		RCC_AHB4ENSETR, 3, 0),
1632 	K_GATE(G_GPIOC,		RCC_AHB4ENSETR, 2, 0),
1633 	K_GATE(G_GPIOB,		RCC_AHB4ENSETR, 1, 0),
1634 	K_GATE(G_GPIOA,		RCC_AHB4ENSETR, 0, 0),
1636 	K_GATE(G_BKPSRAM,	RCC_AHB5ENSETR, 8, 0),
1637 	K_MGATE(G_RNG1,		RCC_AHB5ENSETR, 6, 0),
1638 	K_GATE(G_HASH1,		RCC_AHB5ENSETR, 5, 0),
1639 	K_GATE(G_CRYP1,		RCC_AHB5ENSETR, 4, 0),
1640 	K_GATE(G_GPIOZ,		RCC_AHB5ENSETR, 0, 0),
1642 	K_GATE(G_USBH,		RCC_AHB6ENSETR, 24, 0),
1643 	K_GATE(G_CRC1,		RCC_AHB6ENSETR, 20, 0),
1644 	K_MGATE(G_SDMMC2,	RCC_AHB6ENSETR, 17, 0),
1645 	K_MGATE(G_SDMMC1,	RCC_AHB6ENSETR, 16, 0),
1646 	K_MGATE(G_QSPI,		RCC_AHB6ENSETR, 14, 0),
1647 	K_MGATE(G_FMC,		RCC_AHB6ENSETR, 12, 0),
1648 	K_GATE(G_ETHMAC,	RCC_AHB6ENSETR, 10, 0),
1649 	K_GATE(G_ETHRX,		RCC_AHB6ENSETR, 9, 0),
1650 	K_GATE(G_ETHTX,		RCC_AHB6ENSETR, 8, 0),
1651 	K_GATE(G_ETHCK,		RCC_AHB6ENSETR, 7, 0),
1652 	K_MGATE(G_GPU,		RCC_AHB6ENSETR, 5, 0),
1653 	K_GATE(G_MDMA,		RCC_AHB6ENSETR, 0, 0),
1654 	K_GATE(G_ETHSTP,	RCC_AHB6LPENSETR, 11, 0),
1721 	K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1722 	K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
1723 	K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
1724 	K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
1725 	K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
1726 	K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
1727 	K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
1728 	K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
1729 	K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
1730 	K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
1731 	K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
1732 	K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
1733 	K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
1736 	K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
1737 	K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
1738 	K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
1739 	K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
1740 	K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
1741 	K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
1742 	K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
1743 	K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
1744 	K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
1745 	K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
1746 	K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
1747 	K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
1748 	K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
1749 	K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
1750 	K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
1751 	K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
1752 	K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
1753 	K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
1754 	K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
1755 	K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
1756 	K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
1757 	K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
1762 	GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1765 		 RCC_OCENSETR, 4, 0),
1766 	COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
1767 		  _GATE_MP1(RCC_OCENSETR, 0, 0),
1769 		  _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
1771 	GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1772 	GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1774 	FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1777 	PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
1778 	PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
1779 	PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
1780 	PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
1783 	COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
1784 		  _GATE(RCC_PLL1CR, 4, 0),
1786 		  _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
1788 	COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
1789 		  _GATE(RCC_PLL2CR, 4, 0),
1791 		  _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
1793 	COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
1794 		  _GATE(RCC_PLL2CR, 5, 0),
1796 		  _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
1799 		  _GATE(RCC_PLL2CR, 6, 0),
1801 		  _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
1803 	COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
1804 		  _GATE(RCC_PLL3CR, 4, 0),
1806 		  _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
1808 	COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
1809 		  _GATE(RCC_PLL3CR, 5, 0),
1811 		  _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
1813 	COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
1814 		  _GATE(RCC_PLL3CR, 6, 0),
1816 		  _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
1818 	COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
1819 		  _GATE(RCC_PLL4CR, 4, 0),
1821 		  _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
1823 	COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
1824 		  _GATE(RCC_PLL4CR, 5, 0),
1826 		  _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
1828 	COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
1829 		  _GATE(RCC_PLL4CR, 6, 0),
1831 		  _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
1835 	    RCC_CPERCKSELR, 0, 2, 0),
1838 	     CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
1843 		   _MUX(RCC_ASSCKSELR, 0, 2, 0),
1844 		   _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
1849 		   _MUX(RCC_MSSCKSELR, 0, 2, 0),
1850 		   _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
1852 	DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
1855 	DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
1858 	DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
1861 	DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
1864 	DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
1868 	STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1869 	STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1871 	STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
1880 	STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
1896 	PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
1897 	PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
1898 	PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
1899 	PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
1900 	PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
1901 	PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
1902 	PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
1903 	PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
1904 	PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
1905 	PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
1906 	PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
1907 	PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
1908 	PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
1909 	PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
1910 	PCLK(CEC, "cec", "pclk1", 0, G_CEC),
1911 	PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
1912 	PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
1918 	PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
1919 	PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
1920 	PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
1921 	PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
1922 	PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
1923 	PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
1924 	PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
1925 	PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
1926 	PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
1927 	PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
1928 	PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
1929 	PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
1930 	PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
1931 	PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
1932 	PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
1934 	PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
1935 	PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
1936 	PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
1937 	PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
1938 	PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
1939 	PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
1940 	PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
1941 	PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
1942 	PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
1943 	PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
1944 	PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
1945 	PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1951 	PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1954 	PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
1955 	PCLK(DMA2, "dma2", "ck_mcu",  0, G_DMA2),
1956 	PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
1957 	PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
1958 	PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
1959 	PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
1960 	PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
1961 	PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
1962 	PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
1963 	PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
1964 	PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
1965 	PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
1966 	PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
1967 	PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
1968 	PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
1969 	PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
1970 	PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
1971 	PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
1972 	PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
1973 	PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
1974 	PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
1975 	PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
1976 	PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
1977 	PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
1981 	PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
1983 	PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
1984 	PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
1985 	PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
1986 	PCLK_PDATA(ETHRX, "ethrx", ethrx_src, 0, G_ETHRX),
1987 	PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
1990 	PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
1991 	PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
1992 	PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
1993 	PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
1994 	PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
1995 	PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
1998 	KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
1999 	KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
2000 	KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
2001 	KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
2002 	KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
2003 	KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
2004 	KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
2005 	KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
2007 	KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
2008 	KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
2009 	KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
2010 	KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
2011 	KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
2012 	KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
2013 	KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
2014 	KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
2015 	KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
2016 	KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
2017 	KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
2018 	KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
2019 	KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
2020 	KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
2021 	KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
2022 	KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
2023 	KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
2024 	KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
2025 	KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
2026 	KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
2027 	KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
2028 	KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
2029 	KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
2030 	KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
2031 	KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
2032 	KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
2033 	KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
2034 	KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
2035 	KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
2036 	KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
2037 	KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
2038 	KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
2039 	KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
2040 	KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
2041 	KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
2042 	KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
2045 	MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
2048 	MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
2049 	MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
2057 	MGATE_MP1(ETHCK_K, "ethck_k", "ck_ker_eth", 0, G_ETHCK),
2060 	    CLK_SET_RATE_NO_REPARENT, RCC_ETHCKSELR, 4, 4, 0),
2064 		  _GATE(RCC_BDCR, 20, 0),
2065 		  _MUX(RCC_BDCR, 16, 2, 0),
2066 		  _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
2071 		  _GATE(RCC_MCO1CFGR, 12, 0),
2072 		  _MUX(RCC_MCO1CFGR, 0, 3, 0),
2073 		  _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
2077 		  _GATE(RCC_MCO2CFGR, 12, 0),
2078 		  _MUX(RCC_MCO2CFGR, 0, 3, 0),
2079 		  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
2083 	     RCC_DBGCFGR, 8, 0),
2086 		  _GATE(RCC_DBGCFGR, 9, 0),
2088 		  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
2134 	for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)  in stm32_check_security()
2202 	return 0;  in stm32_register_hw_clk()
2224 	for (n = 0; n < max_binding; n++)  in stm32_rcc_clock_init()
2227 	for (n = 0; n < data->num; n++) {  in stm32_rcc_clock_init()
2273 	return 0;  in stm32_rcc_init()
2281 	base = of_iomap(dev_of_node(dev), 0);  in stm32mp1_rcc_init()
2314 	for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {  in get_clock_deps()
2328 	return 0;  in get_clock_deps()