Lines Matching refs:div_id
209 u16 div_id, in stm32_divider_get_rate() argument
212 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_get_rate()
223 div_id); in stm32_divider_get_rate()
232 u16 div_id, unsigned long rate, in stm32_divider_set_rate() argument
235 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_set_rate()
342 if (div->div_id == NO_STM32_DIV) in clk_stm32_divider_set_rate()
347 ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate); in clk_stm32_divider_set_rate()
360 if (div->div_id == NO_STM32_DIV) in clk_stm32_divider_round_rate()
363 divider = &div->clock_data->dividers[div->div_id]; in clk_stm32_divider_round_rate()
387 if (div->div_id == NO_STM32_DIV) in clk_stm32_divider_recalc_rate()
390 return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate); in clk_stm32_divider_recalc_rate()
406 if (composite->div_id == NO_STM32_DIV) in clk_stm32_composite_set_rate()
412 composite->div_id, rate, parent_rate); in clk_stm32_composite_set_rate()
424 if (composite->div_id == NO_STM32_DIV) in clk_stm32_composite_recalc_rate()
428 composite->div_id, parent_rate); in clk_stm32_composite_recalc_rate()
438 if (composite->div_id == NO_STM32_DIV) in clk_stm32_composite_determine_rate()
441 divider = &composite->clock_data->dividers[composite->div_id]; in clk_stm32_composite_determine_rate()