Lines Matching refs:clock_data

262 	return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);  in clk_stm32_mux_get_parent()
272 stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index); in clk_stm32_mux_set_parent()
292 stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable); in clk_stm32_gate_endisable()
313 return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id); in clk_stm32_gate_is_enabled()
323 stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id); in clk_stm32_gate_disable_unused()
347 ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate); in clk_stm32_divider_set_rate()
363 divider = &div->clock_data->dividers[div->div_id]; in clk_stm32_divider_round_rate()
390 return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate); in clk_stm32_divider_recalc_rate()
411 ret = stm32_divider_set_rate(composite->base, composite->clock_data, in clk_stm32_composite_set_rate()
427 return stm32_divider_get_rate(composite->base, composite->clock_data, in clk_stm32_composite_recalc_rate()
441 divider = &composite->clock_data->dividers[composite->div_id]; in clk_stm32_composite_determine_rate()
474 return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id); in clk_stm32_composite_get_parent()
484 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index); in clk_stm32_composite_set_parent()
488 if (composite->clock_data->is_multi_mux) { in clk_stm32_composite_set_parent()
489 struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw); in clk_stm32_composite_set_parent()
508 return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id); in clk_stm32_composite_is_enabled()
516 const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id]; in clk_stm32_has_safe_mux()
528 if (composite->clock_data->is_multi_mux) { in clk_stm32_set_safe_position_mux()
531 other_mux_hw = composite->clock_data->is_multi_mux(hw); in clk_stm32_set_safe_position_mux()
539 stm32_mux_set_parent(composite->base, composite->clock_data, in clk_stm32_set_safe_position_mux()
554 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel); in clk_stm32_safe_restore_position_mux()
566 stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable); in clk_stm32_composite_gate_endisable()
609 stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id); in clk_stm32_composite_disable_unused()
638 mux->clock_data = data->clock_data; in clk_stm32_mux_register()
659 gate->clock_data = data->clock_data; in clk_stm32_gate_register()
680 div->clock_data = data->clock_data; in clk_stm32_div_register()
701 composite->clock_data = data->clock_data; in clk_stm32_composite_register()