26 #define PLL_BW_GOODREF   (0L)
88 	.nrst	= { CLKGEN_FIELD(0x2f0, 0x1, 0),
89 		    CLKGEN_FIELD(0x2f0, 0x1, 1),
90 		    CLKGEN_FIELD(0x2f0, 0x1, 2),
91 		    CLKGEN_FIELD(0x2f0, 0x1, 3) },
92 	.npda	= CLKGEN_FIELD(0x2f0, 0x1, 12),
93 	.nsb	= { CLKGEN_FIELD(0x2f0, 0x1, 8),
94 		    CLKGEN_FIELD(0x2f0, 0x1, 9),
95 		    CLKGEN_FIELD(0x2f0, 0x1, 10),
96 		    CLKGEN_FIELD(0x2f0, 0x1, 11) },
98 	.nsdiv	= { CLKGEN_FIELD(0x304, 0x1, 24),
99 		    CLKGEN_FIELD(0x308, 0x1, 24),
100 		    CLKGEN_FIELD(0x30c, 0x1, 24),
101 		    CLKGEN_FIELD(0x310, 0x1, 24) },
102 	.mdiv	= { CLKGEN_FIELD(0x304, 0x1f, 15),
103 		    CLKGEN_FIELD(0x308, 0x1f, 15),
104 		    CLKGEN_FIELD(0x30c, 0x1f, 15),
105 		    CLKGEN_FIELD(0x310, 0x1f, 15) },
106 	.en	= { CLKGEN_FIELD(0x2fc, 0x1, 0),
107 		    CLKGEN_FIELD(0x2fc, 0x1, 1),
108 		    CLKGEN_FIELD(0x2fc, 0x1, 2),
109 		    CLKGEN_FIELD(0x2fc, 0x1, 3) },
110 	.ndiv	= CLKGEN_FIELD(0x2f4, 0x7, 16),
111 	.pe	= { CLKGEN_FIELD(0x304, 0x7fff, 0),
112 		    CLKGEN_FIELD(0x308, 0x7fff, 0),
113 		    CLKGEN_FIELD(0x30c, 0x7fff, 0),
114 		    CLKGEN_FIELD(0x310, 0x7fff, 0) },
115 	.sdiv	= { CLKGEN_FIELD(0x304, 0xf, 20),
116 		    CLKGEN_FIELD(0x308, 0xf, 20),
117 		    CLKGEN_FIELD(0x30c, 0xf, 20),
118 		    CLKGEN_FIELD(0x310, 0xf, 20) },
120 	.lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
142 	.nrst	= { CLKGEN_FIELD(0x2a0, 0x1, 0),
143 		    CLKGEN_FIELD(0x2a0, 0x1, 1),
144 		    CLKGEN_FIELD(0x2a0, 0x1, 2),
145 		    CLKGEN_FIELD(0x2a0, 0x1, 3) },
146 	.ndiv	= CLKGEN_FIELD(0x2a4, 0x7, 16),
147 	.pe	= { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
148 		    CLKGEN_FIELD(0x2b8, 0x7fff, 0),
149 		    CLKGEN_FIELD(0x2bc, 0x7fff, 0),
150 		    CLKGEN_FIELD(0x2c0, 0x7fff, 0) },
151 	.sdiv	= { CLKGEN_FIELD(0x2b4, 0xf, 20),
152 		    CLKGEN_FIELD(0x2b8, 0xf, 20),
153 		    CLKGEN_FIELD(0x2bc, 0xf, 20),
154 		    CLKGEN_FIELD(0x2c0, 0xf, 20) },
155 	.npda	= CLKGEN_FIELD(0x2a0, 0x1, 12),
156 	.nsb	= { CLKGEN_FIELD(0x2a0, 0x1, 8),
157 		    CLKGEN_FIELD(0x2a0, 0x1, 9),
158 		    CLKGEN_FIELD(0x2a0, 0x1, 10),
159 		    CLKGEN_FIELD(0x2a0, 0x1, 11) },
161 	.nsdiv	= { CLKGEN_FIELD(0x2b4, 0x1, 24),
162 		    CLKGEN_FIELD(0x2b8, 0x1, 24),
163 		    CLKGEN_FIELD(0x2bc, 0x1, 24),
164 		    CLKGEN_FIELD(0x2c0, 0x1, 24) },
165 	.mdiv	= { CLKGEN_FIELD(0x2b4, 0x1f, 15),
166 		    CLKGEN_FIELD(0x2b8, 0x1f, 15),
167 		    CLKGEN_FIELD(0x2bc, 0x1f, 15),
168 		    CLKGEN_FIELD(0x2c0, 0x1f, 15) },
169 	.en	= { CLKGEN_FIELD(0x2ac, 0x1, 0),
170 		    CLKGEN_FIELD(0x2ac, 0x1, 1),
171 		    CLKGEN_FIELD(0x2ac, 0x1, 2),
172 		    CLKGEN_FIELD(0x2ac, 0x1, 3) },
174 	.lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
255 	unsigned long flags = 0, timeout = jiffies + msecs_to_jiffies(10);  in quadfs_pll_enable()
290 	return 0;  in quadfs_pll_enable()
296 	unsigned long flags = 0;  in quadfs_pll_disable()
308 		CLKGEN_WRITE(pll, nreset, 0);  in quadfs_pll_disable()
329 	return 0;  in clk_fs660c32_vco_get_rate()
336 	unsigned long rate = 0;  in quadfs_pll_fs660c32_recalc_rate()
375 	return 0;  in clk_fs660c32_vco_get_params()
401 	long hwrate = 0;  in quadfs_pll_fs660c32_set_rate()
402 	unsigned long flags = 0;  in quadfs_pll_fs660c32_set_rate()
414 	pr_debug("%s: %s new rate %ld [ndiv=0x%x]\n",  in quadfs_pll_fs660c32_set_rate()
431 	return 0;  in quadfs_pll_fs660c32_set_rate()
540 	CLKGEN_WRITE(fs, en[fs->chan], 0);  in quadfs_fsynth_program_enable()
545 	unsigned long flags = 0;  in quadfs_fsynth_program_rate()
552 	CLKGEN_WRITE(fs, en[fs->chan], 0);  in quadfs_fsynth_program_rate()
571 	unsigned long flags = 0;  in quadfs_fsynth_enable()
583 		CLKGEN_WRITE(fs, nrst[fs->chan], 0);  in quadfs_fsynth_enable()
590 	return 0;  in quadfs_fsynth_enable()
596 	unsigned long flags = 0;  in quadfs_fsynth_disable()
614 	pr_debug("%s: %s enable bit = 0x%x\n",  in quadfs_fsynth_is_enabled()
634 	 *       0        3  in clk_fs660c32_dig_get_rate()
642 	return 0;  in clk_fs660c32_dig_get_rate()
679 	return 0;  in clk_fs660c32_get_pe()
685 	int si;	/* sdiv_reg (8 downto 0) */  in clk_fs660c32_dig_get_params()
689 	unsigned long deviation = ~0;  in clk_fs660c32_dig_get_params()
695 	for (si = 0; (si <= 8) && deviation; si++) {  in clk_fs660c32_dig_get_params()
698 		r1 = clk_fs660c32_get_pe(0, si, &deviation,  in clk_fs660c32_dig_get_params()
714 	if (deviation == ~0) /* No solution found */  in clk_fs660c32_dig_get_params()
717 	/* pe fine tuning if deviation not 0: +/- 2 around computed pe value */  in clk_fs660c32_dig_get_params()
726 			p2 = 0;  in clk_fs660c32_dig_get_params()
743 	return 0;  in clk_fs660c32_dig_get_params()
772 	return 0;  in quadfs_fsynt_get_hw_value_for_recalc()
782 	unsigned long rate = 0;  in quadfs_find_best_rate()
797 	unsigned long rate = 0;  in quadfs_recalc_rate()
805 		return 0;  in quadfs_recalc_rate()
824 	pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n",  in quadfs_round_rate()
859 	memset(&params, 0, sizeof(struct stm_fs));  in quadfs_set_rate()
867 	return 0;  in quadfs_set_rate()
941 	for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) {  in st_of_create_quadfs_fsynths()
944 		unsigned long flags = 0;  in st_of_create_quadfs_fsynths()
960 		if (*clk_name == '\0')  in st_of_create_quadfs_fsynths()
996 	reg = of_iomap(np, 0);  in st_of_quadfs_setup()
999 		reg = of_iomap(parent_np, 0);  in st_of_quadfs_setup()
1007 	clk_parent_name = of_clk_get_parent_name(np, 0);  in st_of_quadfs_setup()