Lines Matching +full:name +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
10 #include <linux/clk-provider.h>
20 const char *name; member
36 /* Pre-divisor's gate */
38 /* Pre-divisor */
56 struct clk_hw *pgate_hw = &flexgen->pgate.hw; in flexgen_enable()
57 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_enable()
73 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_disable()
86 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_is_enabled()
99 struct clk_hw *mux_hw = &flexgen->mux.hw; in flexgen_get_parent()
109 struct clk_hw *mux_hw = &flexgen->mux.hw; in flexgen_set_parent()
128 div = clk_best_div(req->best_parent_rate, req->rate); in flexgen_determine_rate()
131 req->best_parent_rate = req->rate * div; in flexgen_determine_rate()
135 req->rate = req->best_parent_rate / div; in flexgen_determine_rate()
143 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_recalc_rate()
144 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; in flexgen_recalc_rate()
159 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_set_rate()
160 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; in flexgen_set_rate()
161 struct clk_hw *sync_hw = &flexgen->sync.hw; in flexgen_set_rate()
170 if (flexgen->control_mode) { in flexgen_set_rate()
171 reg = readl(config->reg); in flexgen_set_rate()
172 reg &= ~BIT(config->bit_idx); in flexgen_set_rate()
173 writel(reg, config->reg); in flexgen_set_rate()
206 static struct clk *clk_register_flexgen(const char *name, in clk_register_flexgen() argument
218 return ERR_PTR(-ENOMEM); in clk_register_flexgen()
220 init.name = name; in clk_register_flexgen()
231 fgxbar->mux.lock = lock; in clk_register_flexgen()
232 fgxbar->mux.mask = BIT(6) - 1; in clk_register_flexgen()
233 fgxbar->mux.reg = xbar_reg; in clk_register_flexgen()
234 fgxbar->mux.shift = xbar_shift; in clk_register_flexgen()
235 fgxbar->mux.table = NULL; in clk_register_flexgen()
238 /* Pre-divider's gate config (in xbar register)*/ in clk_register_flexgen()
239 fgxbar->pgate.lock = lock; in clk_register_flexgen()
240 fgxbar->pgate.reg = xbar_reg; in clk_register_flexgen()
241 fgxbar->pgate.bit_idx = xbar_shift + 6; in clk_register_flexgen()
243 /* Pre-divider config */ in clk_register_flexgen()
244 fgxbar->pdiv.lock = lock; in clk_register_flexgen()
245 fgxbar->pdiv.reg = reg + 0x58 + idx * 4; in clk_register_flexgen()
246 fgxbar->pdiv.width = 10; in clk_register_flexgen()
249 fgxbar->fgate.lock = lock; in clk_register_flexgen()
250 fgxbar->fgate.reg = fdiv_reg; in clk_register_flexgen()
251 fgxbar->fgate.bit_idx = 6; in clk_register_flexgen()
254 fgxbar->fdiv.lock = lock; in clk_register_flexgen()
255 fgxbar->fdiv.reg = fdiv_reg; in clk_register_flexgen()
256 fgxbar->fdiv.width = 6; in clk_register_flexgen()
259 fgxbar->sync.lock = lock; in clk_register_flexgen()
260 fgxbar->sync.reg = fdiv_reg; in clk_register_flexgen()
261 fgxbar->sync.bit_idx = 7; in clk_register_flexgen()
263 fgxbar->control_mode = mode; in clk_register_flexgen()
265 fgxbar->hw.init = &init; in clk_register_flexgen()
267 clk = clk_register(NULL, &fgxbar->hw); in clk_register_flexgen()
308 { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
309 { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
318 { .name = "clk-icn-gpu", },
319 { .name = "clk-fdma", },
320 { .name = "clk-nand", },
321 { .name = "clk-hva", },
322 { .name = "clk-proc-stfe", },
323 { .name = "clk-proc-tp", },
324 { .name = "clk-rx-icn-dmu", },
325 { .name = "clk-rx-icn-hva", },
327 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
329 { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
330 { .name = "clk-mmc-0", },
331 { .name = "clk-mmc-1", },
332 { .name = "clk-jpegdec", },
334 { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
335 { .name = "clk-ic-bdisp-0", },
336 { .name = "clk-ic-bdisp-1", },
337 { .name = "clk-pp-dmu", },
338 { .name = "clk-vid-dmu", },
339 { .name = "clk-dss-lpc", },
340 { .name = "clk-st231-aud-0", },
341 { .name = "clk-st231-gp-1", },
342 { .name = "clk-st231-dmu", },
344 { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
345 { .name = "clk-tx-icn-disp-1", },
347 { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
348 { .name = "clk-stfe-frc2", },
349 { .name = "clk-eth-phy", },
350 { .name = "clk-eth-ref-phyclk", },
351 { .name = "clk-flash-promip", },
352 { .name = "clk-main-disp", },
353 { .name = "clk-aux-disp", },
354 { .name = "clk-compo-dvp", },
355 { .name = "clk-tx-icn-hades", },
356 { .name = "clk-rx-icn-hades", },
358 { .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL },
359 { .name = "clk-pp-hades", },
360 { .name = "clk-clust-hades", },
361 { .name = "clk-hwpe-hades", },
362 { .name = "clk-fc-hades", },
371 { .name = "clk-icn-gpu", },
372 { .name = "clk-fdma", },
373 { .name = "clk-nand", },
374 { .name = "clk-hva", },
375 { .name = "clk-proc-stfe", },
376 { .name = "clk-tp", },
378 { .name = "clk-rx-icn-dmu", .flags = CLK_IS_CRITICAL },
380 { .name = "clk-rx-icn-hva", .flags = CLK_IS_CRITICAL },
381 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
383 { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
384 { .name = "clk-mmc-0", },
385 { .name = "clk-mmc-1", },
386 { .name = "clk-jpegdec", },
388 { .name = "clk-icn-reg", .flags = CLK_IS_CRITICAL },
389 { .name = "clk-proc-bdisp-0", },
390 { .name = "clk-proc-bdisp-1", },
391 { .name = "clk-pp-dmu", },
392 { .name = "clk-vid-dmu", },
393 { .name = "clk-dss-lpc", },
394 { .name = "clk-st231-aud-0", },
395 { .name = "clk-st231-gp-1", },
396 { .name = "clk-st231-dmu", },
398 { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
400 { .name = "clk-tx-icn-1", .flags = CLK_IS_CRITICAL },
402 { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
403 { .name = "clk-stfe-frc2", },
404 { .name = "clk-eth-phyref", },
405 { .name = "clk-eth-ref-phyclk", },
406 { .name = "clk-flash-promip", },
407 { .name = "clk-main-disp", },
408 { .name = "clk-aux-disp", },
409 { .name = "clk-compo-dvp", },
411 { .name = "clk-tx-icn-hades", .flags = CLK_IS_CRITICAL },
413 { .name = "clk-rx-icn-hades", .flags = CLK_IS_CRITICAL },
415 { .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL },
416 { .name = "clk-pp-hevc", },
417 { .name = "clk-clust-hevc", },
418 { .name = "clk-hwpe-hevc", },
419 { .name = "clk-fc-hevc", },
420 { .name = "clk-proc-mixer", },
421 { .name = "clk-proc-sc", },
422 { .name = "clk-avsp-hevc", },
431 { .name = "clk-pcm-0", },
432 { .name = "clk-pcm-1", },
433 { .name = "clk-pcm-2", },
434 { .name = "clk-spdiff", },
435 { .name = "clk-pcmr10-master", },
436 { .name = "clk-usb2-phy", },
446 { .name = "clk-pix-main-disp", },
447 { .name = "clk-pix-pip", },
448 { .name = "clk-pix-gdp1", },
449 { .name = "clk-pix-gdp2", },
450 { .name = "clk-pix-gdp3", },
451 { .name = "clk-pix-gdp4", },
452 { .name = "clk-pix-aux-disp", },
453 { .name = "clk-denc", },
454 { .name = "clk-pix-hddac", },
455 { .name = "clk-hddac", },
456 { .name = "clk-sddac", },
457 { .name = "clk-pix-dvo", },
458 { .name = "clk-dvo", },
459 { .name = "clk-pix-hdmi", },
460 { .name = "clk-tmds-hdmi", },
461 { .name = "clk-ref-hdmiphy", },
472 { .name = "clk-pix-main-disp", },
473 { .name = "", },
474 { .name = "", },
475 { .name = "", },
476 { .name = "", },
477 { .name = "clk-tmds-hdmi-div2", },
478 { .name = "clk-pix-aux-disp", },
479 { .name = "clk-denc", },
480 { .name = "clk-pix-hddac", },
481 { .name = "clk-hddac", },
482 { .name = "clk-sddac", },
483 { .name = "clk-pix-dvo", },
484 { .name = "clk-dvo", },
485 { .name = "clk-pix-hdmi", },
486 { .name = "clk-tmds-hdmi", },
487 { .name = "clk-ref-hdmiphy", },
488 { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
489 { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
490 { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
491 { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
492 { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
493 { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
494 { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", },
495 { .name = "", }, { .name = "", }, { .name = "", },
496 { .name = "clk-vp9", },
507 { .name = "clk-stfe-frc1", },
508 { .name = "clk-tsout-0", },
509 { .name = "clk-tsout-1", },
510 { .name = "clk-mchi", },
511 { .name = "clk-vsens-compo", },
512 { .name = "clk-frc1-remote", },
513 { .name = "clk-lpc-0", },
514 { .name = "clk-lpc-1", },
524 .compatible = "st,flexgen-audio",
528 .compatible = "st,flexgen-video",
532 .compatible = "st,flexgen-stih410-a0",
536 .compatible = "st,flexgen-stih410-c0",
540 .compatible = "st,flexgen-stih418-c0",
544 .compatible = "st,flexgen-stih410-d0",
548 .compatible = "st,flexgen-stih407-d2",
552 .compatible = "st,flexgen-stih418-d2",
556 .compatible = "st,flexgen-stih407-d3",
594 data = (struct clkgen_data *)match->data; in st_of_flexgen_setup()
595 flex_flags = data->flags; in st_of_flexgen_setup()
596 clk_mode = data->mode; in st_of_flexgen_setup()
604 if (!data || !data->outputs_nb || !data->outputs) { in st_of_flexgen_setup()
605 ret = of_property_count_strings(np, "clock-output-names"); in st_of_flexgen_setup()
608 __func__, clk_data->clk_num); in st_of_flexgen_setup()
611 clk_data->clk_num = ret; in st_of_flexgen_setup()
613 clk_data->clk_num = data->outputs_nb; in st_of_flexgen_setup()
615 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), in st_of_flexgen_setup()
617 if (!clk_data->clks) in st_of_flexgen_setup()
626 for (i = 0; i < clk_data->clk_num; i++) { in st_of_flexgen_setup()
629 if (!data || !data->outputs_nb || !data->outputs) { in st_of_flexgen_setup()
631 "clock-output-names", in st_of_flexgen_setup()
637 clk_name = data->outputs[i].name; in st_of_flexgen_setup()
638 flex_flags = data->flags | data->outputs[i].flags; in st_of_flexgen_setup()
642 * If we read an empty clock name then the output is unused in st_of_flexgen_setup()
653 clk_data->clks[i] = clk; in st_of_flexgen_setup()
664 kfree(clk_data->clks); in st_of_flexgen_setup()