Lines Matching +full:div +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/spear1340_clock.c
12 #include <linux/clk/spear.h>
16 #include "clk.h"
175 /* vco-pll4 rate configuration table, in ascending order of rates */
188 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
189 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
190 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
191 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
192 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
193 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
205 * --------------------------------------------------------------------
206 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
207 * --------------------------------------------------------------------
212 * --------------------------------------------------------------------
218 * --------------------------------------------------------------------
224 * --------------------------------------------------------------------
230 * --------------------------------------------------------------------
236 * --------------------------------------------------------------------
240 {.div = 0x08000},
241 {.div = 0x06a38},
242 {.div = 0x06666},
243 {.div = 0x06000},
244 {.div = 0x054FD},
245 {.div = 0x05000},
246 {.div = 0x04D18},
247 {.div = 0x04CCE},
248 {.div = 0x04000},
249 {.div = 0x039D5},
250 {.div = 0x0351E},
251 {.div = 0x03333},
252 {.div = 0x03031},
253 {.div = 0x03000},
254 {.div = 0x02A7E},
255 {.div = 0x02800},
256 {.div = 0x0268D},
257 {.div = 0x02666},
258 {.div = 0x02000},
291 /* For gmac phy input clk */
300 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
301 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
302 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
303 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
304 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
305 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
306 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
307 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
308 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
309 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
310 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
311 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
312 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
313 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
314 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
315 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
316 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
317 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
318 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
319 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
349 /* For parent clk = 49.152 MHz */
356 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
357 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
361 /* For parent clk = 49.152 MHz */
385 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
386 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
387 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
388 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
389 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
390 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
391 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
392 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
393 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
394 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
395 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
396 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
397 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
398 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
399 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
400 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
401 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
402 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
403 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
404 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
405 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
406 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
407 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
408 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
409 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
441 struct clk *clk, *clk1;
443 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
444 clk_register_clkdev(clk, "osc_32k_clk", NULL);
446 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
447 clk_register_clkdev(clk, "osc_24m_clk", NULL);
449 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
450 clk_register_clkdev(clk, "osc_25m_clk", NULL);
452 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
453 clk_register_clkdev(clk, "gmii_pad_clk", NULL);
455 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
457 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
459 /* clock derived from 32 KHz osc clk */
460 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
463 clk_register_clkdev(clk, NULL, "e0580000.rtc");
465 /* clock derived from 24 or 25 MHz osc clk */
466 /* vco-pll */
467 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
471 clk_register_clkdev(clk, "vco1_mclk", NULL);
472 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
475 clk_register_clkdev(clk, "vco1_clk", NULL);
478 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
482 clk_register_clkdev(clk, "vco2_mclk", NULL);
483 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
486 clk_register_clkdev(clk, "vco2_clk", NULL);
489 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
493 clk_register_clkdev(clk, "vco3_mclk", NULL);
494 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
497 clk_register_clkdev(clk, "vco3_clk", NULL);
500 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
503 clk_register_clkdev(clk, "vco4_clk", NULL);
506 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
508 clk_register_clkdev(clk, "pll5_clk", NULL);
510 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
512 clk_register_clkdev(clk, "pll6_clk", NULL);
514 /* vco div n clocks */
515 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
517 clk_register_clkdev(clk, "vco1div2_clk", NULL);
519 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
521 clk_register_clkdev(clk, "vco1div4_clk", NULL);
523 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
525 clk_register_clkdev(clk, "vco2div2_clk", NULL);
527 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
529 clk_register_clkdev(clk, "vco3div2_clk", NULL);
534 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
537 clk_register_clkdev(clk, NULL, "e07008c4.thermal");
539 /* clock derived from pll4 clk */
540 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
542 clk_register_clkdev(clk, "ddr_clk", NULL);
544 /* clock derived from pll1 clk */
545 clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0,
548 clk_register_clkdev(clk, "sys_syn_clk", NULL);
550 clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0,
553 clk_register_clkdev(clk, "amba_syn_clk", NULL);
555 clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
559 clk_register_clkdev(clk, "sys_mclk", NULL);
561 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
563 clk_register_clkdev(clk, "cpu_clk", NULL);
565 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
567 clk_register_clkdev(clk, "cpu_div3_clk", NULL);
569 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
571 clk_register_clkdev(clk, NULL, "ec800620.wdt");
573 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
575 clk_register_clkdev(clk, NULL, "smp_twd");
577 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
581 clk_register_clkdev(clk, "ahb_clk", NULL);
583 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
585 clk_register_clkdev(clk, "apb_clk", NULL);
588 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
592 clk_register_clkdev(clk, "gpt0_mclk", NULL);
593 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
596 clk_register_clkdev(clk, NULL, "gpt0");
598 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
602 clk_register_clkdev(clk, "gpt1_mclk", NULL);
603 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
606 clk_register_clkdev(clk, NULL, "gpt1");
608 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
612 clk_register_clkdev(clk, "gpt2_mclk", NULL);
613 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
616 clk_register_clkdev(clk, NULL, "gpt2");
618 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
622 clk_register_clkdev(clk, "gpt3_mclk", NULL);
623 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
626 clk_register_clkdev(clk, NULL, "gpt3");
629 clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk",
632 clk_register_clkdev(clk, "uart0_syn_clk", NULL);
635 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
640 clk_register_clkdev(clk, "uart0_mclk", NULL);
642 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
645 clk_register_clkdev(clk, NULL, "e0000000.serial");
647 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
650 clk_register_clkdev(clk, "uart1_syn_clk", NULL);
653 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
657 clk_register_clkdev(clk, "uart1_mclk", NULL);
659 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
662 clk_register_clkdev(clk, NULL, "b4100000.serial");
664 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
667 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
670 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
673 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
675 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
678 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
681 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
684 clk_register_clkdev(clk, NULL, "b2800000.cf");
685 clk_register_clkdev(clk, NULL, "arasan_xd");
687 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0,
690 clk_register_clkdev(clk, "c3_syn_clk", NULL);
693 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
698 clk_register_clkdev(clk, "c3_mclk", NULL);
700 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT,
703 clk_register_clkdev(clk, NULL, "e1800000.c3");
706 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
711 clk_register_clkdev(clk, "phy_input_mclk", NULL);
713 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
716 clk_register_clkdev(clk, "phy_syn_clk", NULL);
719 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
723 clk_register_clkdev(clk, "stmmacphy.0", NULL);
726 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
731 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
733 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
736 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
738 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
743 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
745 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
748 clk_register_clkdev(clk, NULL, "e1000000.clcd");
751 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
755 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
757 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
761 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
763 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
768 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
770 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
773 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
775 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk",
779 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
782 /* clock derived from ahb clk */
783 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
786 clk_register_clkdev(clk, NULL, "e0280000.i2c");
788 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
791 clk_register_clkdev(clk, NULL, "b4000000.i2c");
793 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
796 clk_register_clkdev(clk, NULL, "ea800000.dma");
797 clk_register_clkdev(clk, NULL, "eb000000.dma");
799 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
802 clk_register_clkdev(clk, NULL, "e2000000.eth");
804 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
807 clk_register_clkdev(clk, NULL, "b0000000.flash");
809 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
812 clk_register_clkdev(clk, NULL, "ea000000.flash");
814 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
817 clk_register_clkdev(clk, NULL, "e4000000.ohci");
818 clk_register_clkdev(clk, NULL, "e4800000.ehci");
820 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
823 clk_register_clkdev(clk, NULL, "e5000000.ohci");
824 clk_register_clkdev(clk, NULL, "e5800000.ehci");
826 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
829 clk_register_clkdev(clk, NULL, "e3800000.otg");
831 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
834 clk_register_clkdev(clk, NULL, "b1000000.pcie");
835 clk_register_clkdev(clk, NULL, "b1000000.ahci");
837 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
840 clk_register_clkdev(clk, "sysram0_clk", NULL);
842 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
845 clk_register_clkdev(clk, "sysram1_clk", NULL);
847 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
850 clk_register_clkdev(clk, "adc_syn_clk", NULL);
853 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
856 clk_register_clkdev(clk, NULL, "e0080000.adc");
858 /* clock derived from apb clk */
859 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
862 clk_register_clkdev(clk, NULL, "e0100000.spi");
864 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
867 clk_register_clkdev(clk, NULL, "e0600000.gpio");
869 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
872 clk_register_clkdev(clk, NULL, "e0680000.gpio");
874 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
877 clk_register_clkdev(clk, NULL, "b2400000.i2s-play");
879 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
882 clk_register_clkdev(clk, NULL, "b2000000.i2s-rec");
884 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
887 clk_register_clkdev(clk, NULL, "e0300000.kbd");
890 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
895 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
897 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
902 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
904 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0,
907 clk_register_clkdev(clk, "gen_syn0_clk", NULL);
909 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0,
912 clk_register_clkdev(clk, "gen_syn1_clk", NULL);
914 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0,
917 clk_register_clkdev(clk, "gen_syn2_clk", NULL);
919 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0,
922 clk_register_clkdev(clk, "gen_syn3_clk", NULL);
924 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk",
927 clk_register_clkdev(clk, NULL, "mali");
929 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
932 clk_register_clkdev(clk, NULL, "spear_cec.0");
934 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
937 clk_register_clkdev(clk, NULL, "spear_cec.1");
939 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
944 clk_register_clkdev(clk, "spdif_out_mclk", NULL);
946 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk",
949 clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
951 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
956 clk_register_clkdev(clk, "spdif_in_mclk", NULL);
958 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk",
961 clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
963 clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
966 clk_register_clkdev(clk, NULL, "acp_clk");
968 clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
971 clk_register_clkdev(clk, NULL, "e2800000.gpio");
973 clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
976 clk_register_clkdev(clk, NULL, "video_dec");
978 clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
981 clk_register_clkdev(clk, NULL, "video_enc");
983 clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
986 clk_register_clkdev(clk, NULL, "spear_vip");
988 clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
991 clk_register_clkdev(clk, NULL, "d0200000.cam0");
993 clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
996 clk_register_clkdev(clk, NULL, "d0300000.cam1");
998 clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
1001 clk_register_clkdev(clk, NULL, "d0400000.cam2");
1003 clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
1006 clk_register_clkdev(clk, NULL, "d0500000.cam3");
1008 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
1011 clk_register_clkdev(clk, NULL, "e0180000.pwm");