94 static inline struct sg2044_div *hw_to_sg2044_div(struct clk_hw *hw)  in hw_to_sg2044_div()
100 static u32 sg2044_div_get_reg_div(u32 reg, struct sg2044_div_internal *div)  in sg2044_div_get_reg_div()
108 static unsigned long _sg2044_div_recalc_rate(struct sg2044_clk_common *common,  in _sg2044_div_recalc_rate()
119 static unsigned long sg2044_div_recalc_rate(struct clk_hw *hw,  in sg2044_div_recalc_rate()
128 static int _sg2044_div_determine_rate(struct sg2044_clk_common *common,  in _sg2044_div_determine_rate()
145 static int sg2044_div_determine_rate(struct clk_hw *hw,  in sg2044_div_determine_rate()
153 static void sg2044_div_set_reg_div(struct sg2044_clk_common *common,  in sg2044_div_set_reg_div()
177 static int sg2044_div_set_rate(struct clk_hw *hw,  in sg2044_div_set_rate()
193 static int sg2044_div_enable(struct clk_hw *hw)  in sg2044_div_enable()
208 static void sg2044_div_disable(struct clk_hw *hw)  in sg2044_div_disable()
221 static int sg2044_div_is_enabled(struct clk_hw *hw)  in sg2044_div_is_enabled()
228 static const struct clk_ops sg2044_gateable_div_ops = {
237 static const struct clk_ops sg2044_div_ops = {
243 static const struct clk_ops sg2044_div_ro_ops = {
248 static inline struct sg2044_mux *hw_to_sg2044_mux(struct clk_hw *hw)  in hw_to_sg2044_mux()
254 static inline struct sg2044_mux *nb_to_sg2044_mux(struct notifier_block *nb)  in nb_to_sg2044_mux()
259 static const u32 sg2044_mux_table[] = {0, 1};
261 static int sg2044_mux_notifier_cb(struct notifier_block *nb,  in sg2044_mux_notifier_cb()
282 static inline struct sg2044_gate *hw_to_sg2044_gate(struct clk_hw *hw)  in hw_to_sg2044_gate()
392 static const struct clk_parent_data clk_fpll0_parent[] = {
396 static const struct clk_parent_data clk_fpll1_parent[] = {
400 static const struct clk_parent_data clk_fpll2_parent[] = {
404 static const struct clk_parent_data clk_dpll0_parent[] = {
408 static const struct clk_parent_data clk_dpll1_parent[] = {
412 static const struct clk_parent_data clk_dpll2_parent[] = {
416 static const struct clk_parent_data clk_dpll3_parent[] = {
420 static const struct clk_parent_data clk_dpll4_parent[] = {
424 static const struct clk_parent_data clk_dpll5_parent[] = {
428 static const struct clk_parent_data clk_dpll6_parent[] = {
432 static const struct clk_parent_data clk_dpll7_parent[] = {
436 static const struct clk_parent_data clk_mpll0_parent[] = {
440 static const struct clk_parent_data clk_mpll1_parent[] = {
444 static const struct clk_parent_data clk_mpll2_parent[] = {
448 static const struct clk_parent_data clk_mpll3_parent[] = {
452 static const struct clk_parent_data clk_mpll4_parent[] = {
456 static const struct clk_parent_data clk_mpll5_parent[] = {
460 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_AP_SYS_FIXED, clk_div_ap_sys_fixed,
467 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_AP_SYS_MAIN, clk_div_ap_sys_main,
474 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_RP_SYS_FIXED, clk_div_rp_sys_fixed,
481 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_RP_SYS_MAIN, clk_div_rp_sys_main,
488 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_TPU_SYS_FIXED, clk_div_tpu_sys_fixed,
495 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_TPU_SYS_MAIN, clk_div_tpu_sys_main,
502 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_NOC_SYS_FIXED, clk_div_noc_sys_fixed,
509 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_NOC_SYS_MAIN, clk_div_noc_sys_main,
516 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC0_FIXED, clk_div_vc_src0_fixed,
523 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC0_MAIN, clk_div_vc_src0_main,
530 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC1_FIXED, clk_div_vc_src1_fixed,
537 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC1_MAIN, clk_div_vc_src1_main,
544 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_CXP_MAC_FIXED, clk_div_cxp_mac_fixed,
551 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_CXP_MAC_MAIN, clk_div_cxp_mac_main,
558 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR0_FIXED, clk_div_ddr0_fixed,
564 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR0_MAIN, clk_div_ddr0_main,
570 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR1_FIXED, clk_div_ddr1_fixed,
576 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR1_MAIN, clk_div_ddr1_main,
582 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR2_FIXED, clk_div_ddr2_fixed,
588 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR2_MAIN, clk_div_ddr2_main,
594 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR3_FIXED, clk_div_ddr3_fixed,
600 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR3_MAIN, clk_div_ddr3_main,
606 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR4_FIXED, clk_div_ddr4_fixed,
612 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR4_MAIN, clk_div_ddr4_main,
618 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR5_FIXED, clk_div_ddr5_fixed,
624 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR5_MAIN, clk_div_ddr5_main,
630 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR6_FIXED, clk_div_ddr6_fixed,
636 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR6_MAIN, clk_div_ddr6_main,
642 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR7_FIXED, clk_div_ddr7_fixed,
648 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR7_MAIN, clk_div_ddr7_main,
654 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TOP_50M, clk_div_top_50m,
660 static const struct clk_hw *clk_div_top_50m_parent[] = {
664 static DEFINE_SG2044_DIV_RO(CLK_DIV_TOP_AXI0, clk_div_top_axi0,
670 static const struct clk_hw *clk_div_top_axi0_parent[] = {
674 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TOP_AXI_HSPERI, clk_div_top_axi_hsperi,
680 static const struct clk_hw *clk_div_top_axi_hsperi_parent[] = {
684 static DEFINE_SG2044_DIV(CLK_DIV_TIMER0, clk_div_timer0,
690 static DEFINE_SG2044_DIV(CLK_DIV_TIMER1, clk_div_timer1,
696 static DEFINE_SG2044_DIV(CLK_DIV_TIMER2, clk_div_timer2,
702 static DEFINE_SG2044_DIV(CLK_DIV_TIMER3, clk_div_timer3,
708 static DEFINE_SG2044_DIV(CLK_DIV_TIMER4, clk_div_timer4,
714 static DEFINE_SG2044_DIV(CLK_DIV_TIMER5, clk_div_timer5,
720 static DEFINE_SG2044_DIV(CLK_DIV_TIMER6, clk_div_timer6,
726 static DEFINE_SG2044_DIV(CLK_DIV_TIMER7, clk_div_timer7,
732 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_CXP_TEST_PHY, clk_div_cxp_test_phy,
738 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_CXP_TEST_ETH_PHY, clk_div_cxp_test_eth_phy,
744 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_C2C0_TEST_PHY, clk_div_c2c0_test_phy,
750 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_C2C1_TEST_PHY, clk_div_c2c1_test_phy,
756 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PCIE_1G, clk_div_pcie_1g,
762 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_UART_500M, clk_div_uart_500m,
768 static DEFINE_SG2044_DIV(CLK_DIV_GPIO_DB, clk_div_gpio_db,
774 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_SD, clk_div_sd,
780 static DEFINE_SG2044_DIV(CLK_DIV_SD_100K, clk_div_sd_100k,
786 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_EMMC, clk_div_emmc,
792 static DEFINE_SG2044_DIV(CLK_DIV_EMMC_100K, clk_div_emmc_100k,
798 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_EFUSE, clk_div_efuse,
804 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TX_ETH0, clk_div_tx_eth0,
810 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PTP_REF_I_ETH0, clk_div_ptp_ref_i_eth0,
816 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_REF_ETH0, clk_div_ref_eth0,
822 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PKA, clk_div_pka,
828 static const struct clk_parent_data clk_mux_ddr0_parents[] = {
833 static DEFINE_SG2044_MUX(CLK_MUX_DDR0, clk_mux_ddr0,
838 static const struct clk_parent_data clk_mux_ddr1_parents[] = {
843 static DEFINE_SG2044_MUX(CLK_MUX_DDR1, clk_mux_ddr1,
848 static const struct clk_parent_data clk_mux_ddr2_parents[] = {
853 static DEFINE_SG2044_MUX(CLK_MUX_DDR2, clk_mux_ddr2,
858 static const struct clk_parent_data clk_mux_ddr3_parents[] = {
863 static DEFINE_SG2044_MUX(CLK_MUX_DDR3, clk_mux_ddr3,
868 static const struct clk_parent_data clk_mux_ddr4_parents[] = {
873 static DEFINE_SG2044_MUX(CLK_MUX_DDR4, clk_mux_ddr4,
878 static const struct clk_parent_data clk_mux_ddr5_parents[] = {
883 static DEFINE_SG2044_MUX(CLK_MUX_DDR5, clk_mux_ddr5,
888 static const struct clk_parent_data clk_mux_ddr6_parents[] = {
893 static DEFINE_SG2044_MUX(CLK_MUX_DDR6, clk_mux_ddr6,
898 static const struct clk_parent_data clk_mux_ddr7_parents[] = {
903 static DEFINE_SG2044_MUX(CLK_MUX_DDR7, clk_mux_ddr7,
908 static const struct clk_parent_data clk_mux_noc_sys_parents[] = {
913 static DEFINE_SG2044_MUX(CLK_MUX_NOC_SYS, clk_mux_noc_sys,
918 static const struct clk_parent_data clk_mux_tpu_sys_parents[] = {
923 static DEFINE_SG2044_MUX(CLK_MUX_TPU_SYS, clk_mux_tpu_sys,
928 static const struct clk_parent_data clk_mux_rp_sys_parents[] = {
933 static DEFINE_SG2044_MUX(CLK_MUX_RP_SYS, clk_mux_rp_sys,
938 static const struct clk_parent_data clk_mux_ap_sys_parents[] = {
943 static DEFINE_SG2044_MUX(CLK_MUX_AP_SYS, clk_mux_ap_sys,
948 static const struct clk_parent_data clk_mux_vc_src0_parents[] = {
953 static DEFINE_SG2044_MUX(CLK_MUX_VC_SRC0, clk_mux_vc_src0,
958 static const struct clk_parent_data clk_mux_vc_src1_parents[] = {
963 static DEFINE_SG2044_MUX(CLK_MUX_VC_SRC1, clk_mux_vc_src1,
968 static const struct clk_parent_data clk_mux_cxp_mac_parents[] = {
973 static DEFINE_SG2044_MUX(CLK_MUX_CXP_MAC, clk_mux_cxp_mac,
978 static const struct clk_hw *clk_gate_ap_sys_parent[] = {
982 static DEFINE_SG2044_GATE(CLK_GATE_AP_SYS, clk_gate_ap_sys,
987 static const struct clk_hw *clk_gate_rp_sys_parent[] = {
991 static DEFINE_SG2044_GATE(CLK_GATE_RP_SYS, clk_gate_rp_sys,
996 static const struct clk_hw *clk_gate_tpu_sys_parent[] = {
1000 static DEFINE_SG2044_GATE(CLK_GATE_TPU_SYS, clk_gate_tpu_sys,
1005 static const struct clk_hw *clk_gate_noc_sys_parent[] = {
1009 static DEFINE_SG2044_GATE(CLK_GATE_NOC_SYS, clk_gate_noc_sys,
1014 static const struct clk_hw *clk_gate_vc_src0_parent[] = {
1018 static DEFINE_SG2044_GATE(CLK_GATE_VC_SRC0, clk_gate_vc_src0,
1023 static const struct clk_hw *clk_gate_vc_src1_parent[] = {
1027 static DEFINE_SG2044_GATE(CLK_GATE_VC_SRC1, clk_gate_vc_src1,
1032 static const struct clk_hw *clk_gate_ddr0_parent[] = {
1036 static DEFINE_SG2044_GATE(CLK_GATE_DDR0, clk_gate_ddr0,
1041 static const struct clk_hw *clk_gate_ddr1_parent[] = {
1045 static DEFINE_SG2044_GATE(CLK_GATE_DDR1, clk_gate_ddr1,
1050 static const struct clk_hw *clk_gate_ddr2_parent[] = {
1054 static DEFINE_SG2044_GATE(CLK_GATE_DDR2, clk_gate_ddr2,
1059 static const struct clk_hw *clk_gate_ddr3_parent[] = {
1063 static DEFINE_SG2044_GATE(CLK_GATE_DDR3, clk_gate_ddr3,
1068 static const struct clk_hw *clk_gate_ddr4_parent[] = {
1072 static DEFINE_SG2044_GATE(CLK_GATE_DDR4, clk_gate_ddr4,
1077 static const struct clk_hw *clk_gate_ddr5_parent[] = {
1081 static DEFINE_SG2044_GATE(CLK_GATE_DDR5, clk_gate_ddr5,
1086 static const struct clk_hw *clk_gate_ddr6_parent[] = {
1090 static DEFINE_SG2044_GATE(CLK_GATE_DDR6, clk_gate_ddr6,
1095 static const struct clk_hw *clk_gate_ddr7_parent[] = {
1099 static DEFINE_SG2044_GATE(CLK_GATE_DDR7, clk_gate_ddr7,
1104 static const struct clk_hw *clk_gate_top_50m_parent[] = {
1108 static DEFINE_SG2044_GATE(CLK_GATE_TOP_50M, clk_gate_top_50m,
1113 static const struct clk_hw *clk_gate_sc_rx_parent[] = {
1117 static DEFINE_SG2044_GATE(CLK_GATE_SC_RX, clk_gate_sc_rx,
1122 static const struct clk_hw *clk_gate_sc_rx_x0y1_parent[] = {
1126 static DEFINE_SG2044_GATE(CLK_GATE_SC_RX_X0Y1, clk_gate_sc_rx_x0y1,
1131 static DEFINE_SG2044_GATE(CLK_GATE_TOP_AXI0, clk_gate_top_axi0,
1136 static const struct clk_hw *clk_gate_mailbox_intc_parent[] = {
1140 static DEFINE_SG2044_GATE(CLK_GATE_INTC0, clk_gate_intc0,
1145 static DEFINE_SG2044_GATE(CLK_GATE_INTC1, clk_gate_intc1,
1150 static DEFINE_SG2044_GATE(CLK_GATE_INTC2, clk_gate_intc2,
1155 static DEFINE_SG2044_GATE(CLK_GATE_INTC3, clk_gate_intc3,
1160 static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX0, clk_gate_mailbox0,
1165 static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX1, clk_gate_mailbox1,
1170 static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX2, clk_gate_mailbox2,
1175 static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX3, clk_gate_mailbox3,
1180 static DEFINE_SG2044_GATE(CLK_GATE_TOP_AXI_HSPERI, clk_gate_top_axi_hsperi,
1185 static DEFINE_SG2044_GATE(CLK_GATE_APB_TIMER, clk_gate_apb_timer,
1190 static const struct clk_hw *clk_gate_timer0_parent[] = {
1194 static DEFINE_SG2044_GATE(CLK_GATE_TIMER0, clk_gate_timer0,
1199 static const struct clk_hw *clk_gate_timer1_parent[] = {
1203 static DEFINE_SG2044_GATE(CLK_GATE_TIMER1, clk_gate_timer1,
1208 static const struct clk_hw *clk_gate_timer2_parent[] = {
1212 static DEFINE_SG2044_GATE(CLK_GATE_TIMER2, clk_gate_timer2,
1217 static const struct clk_hw *clk_gate_timer3_parent[] = {
1221 static DEFINE_SG2044_GATE(CLK_GATE_TIMER3, clk_gate_timer3,
1226 static const struct clk_hw *clk_gate_timer4_parent[] = {
1230 static DEFINE_SG2044_GATE(CLK_GATE_TIMER4, clk_gate_timer4,
1235 static const struct clk_hw *clk_gate_timer5_parent[] = {
1239 static DEFINE_SG2044_GATE(CLK_GATE_TIMER5, clk_gate_timer5,
1244 static const struct clk_hw *clk_gate_timer6_parent[] = {
1248 static DEFINE_SG2044_GATE(CLK_GATE_TIMER6, clk_gate_timer6,
1253 static const struct clk_hw *clk_gate_timer7_parent[] = {
1257 static DEFINE_SG2044_GATE(CLK_GATE_TIMER7, clk_gate_timer7,
1262 static DEFINE_SG2044_GATE(CLK_GATE_CXP_CFG, clk_gate_cxp_cfg,
1267 static const struct clk_hw *clk_gate_cxp_mac_parent[] = {
1271 static DEFINE_SG2044_GATE(CLK_GATE_CXP_MAC, clk_gate_cxp_mac,
1276 static const struct clk_hw *clk_gate_cxp_test_phy_parent[] = {
1280 static DEFINE_SG2044_GATE(CLK_GATE_CXP_TEST_PHY, clk_gate_cxp_test_phy,
1285 static const struct clk_hw *clk_gate_cxp_test_eth_phy_parent[] = {
1289 static DEFINE_SG2044_GATE(CLK_GATE_CXP_TEST_ETH_PHY, clk_gate_cxp_test_eth_phy,
1294 static const struct clk_hw *clk_gate_pcie_1g_parent[] = {
1298 static DEFINE_SG2044_GATE(CLK_GATE_PCIE_1G, clk_gate_pcie_1g,
1303 static const struct clk_hw *clk_gate_c2c0_test_phy_parent[] = {
1307 static DEFINE_SG2044_GATE(CLK_GATE_C2C0_TEST_PHY, clk_gate_c2c0_test_phy,
1312 static const struct clk_hw *clk_gate_c2c1_test_phy_parent[] = {
1316 static DEFINE_SG2044_GATE(CLK_GATE_C2C1_TEST_PHY, clk_gate_c2c1_test_phy,
1321 static const struct clk_hw *clk_gate_uart_500m_parent[] = {
1325 static DEFINE_SG2044_GATE(CLK_GATE_UART_500M, clk_gate_uart_500m,
1330 static DEFINE_SG2044_GATE(CLK_GATE_APB_UART, clk_gate_apb_uart,
1335 static DEFINE_SG2044_GATE(CLK_GATE_APB_SPI, clk_gate_apb_spi,
1340 static DEFINE_SG2044_GATE(CLK_GATE_AHB_SPIFMC, clk_gate_ahb_spifmc,
1345 static DEFINE_SG2044_GATE(CLK_GATE_APB_I2C, clk_gate_apb_i2c,
1350 static DEFINE_SG2044_GATE(CLK_GATE_AXI_DBG_I2C, clk_gate_axi_dbg_i2c,
1355 static const struct clk_hw *clk_gate_gpio_db_parent[] = {
1359 static DEFINE_SG2044_GATE(CLK_GATE_GPIO_DB, clk_gate_gpio_db,
1364 static DEFINE_SG2044_GATE(CLK_GATE_APB_GPIO_INTR, clk_gate_apb_gpio_intr,
1369 static DEFINE_SG2044_GATE(CLK_GATE_APB_GPIO, clk_gate_apb_gpio,
1374 static const struct clk_hw *clk_gate_sd_parent[] = {
1378 static DEFINE_SG2044_GATE(CLK_GATE_SD, clk_gate_sd,
1383 static DEFINE_SG2044_GATE(CLK_GATE_AXI_SD, clk_gate_axi_sd,
1388 static const struct clk_hw *clk_gate_sd_100k_parent[] = {
1392 static DEFINE_SG2044_GATE(CLK_GATE_SD_100K, clk_gate_sd_100k,
1397 static const struct clk_hw *clk_gate_emmc_parent[] = {
1401 static DEFINE_SG2044_GATE(CLK_GATE_EMMC, clk_gate_emmc,
1406 static DEFINE_SG2044_GATE(CLK_GATE_AXI_EMMC, clk_gate_axi_emmc,
1411 static const struct clk_hw *clk_gate_emmc_100k_parent[] = {
1415 static DEFINE_SG2044_GATE(CLK_GATE_EMMC_100K, clk_gate_emmc_100k,
1420 static const struct clk_hw *clk_gate_efuse_parent[] = {
1424 static DEFINE_SG2044_GATE(CLK_GATE_EFUSE, clk_gate_efuse,
1429 static DEFINE_SG2044_GATE(CLK_GATE_APB_EFUSE, clk_gate_apb_efuse,
1434 static DEFINE_SG2044_GATE(CLK_GATE_SYSDMA_AXI, clk_gate_sysdma_axi,
1439 static const struct clk_hw *clk_gate_tx_eth0_parent[] = {
1443 static DEFINE_SG2044_GATE(CLK_GATE_TX_ETH0, clk_gate_tx_eth0,
1448 static DEFINE_SG2044_GATE(CLK_GATE_AXI_ETH0, clk_gate_axi_eth0,
1453 static const struct clk_hw *clk_gate_ptp_ref_i_eth0_parent[] = {
1457 static DEFINE_SG2044_GATE(CLK_GATE_PTP_REF_I_ETH0, clk_gate_ptp_ref_i_eth0,
1462 static const struct clk_hw *clk_gate_ref_eth0_parent[] = {
1466 static DEFINE_SG2044_GATE(CLK_GATE_REF_ETH0, clk_gate_ref_eth0,
1471 static DEFINE_SG2044_GATE(CLK_GATE_APB_RTC, clk_gate_apb_rtc,
1476 static DEFINE_SG2044_GATE(CLK_GATE_APB_PWM, clk_gate_apb_pwm,
1481 static DEFINE_SG2044_GATE(CLK_GATE_APB_WDT, clk_gate_apb_wdt,
1486 static DEFINE_SG2044_GATE(CLK_GATE_AXI_SRAM, clk_gate_axi_sram,
1491 static DEFINE_SG2044_GATE(CLK_GATE_AHB_ROM, clk_gate_ahb_rom,
1496 static const struct clk_hw *clk_gate_pka_parent[] = {
1500 static DEFINE_SG2044_GATE(CLK_GATE_PKA, clk_gate_pka,
1505 static struct sg2044_clk_common * const sg2044_div_commons[] = {
1565 static struct sg2044_clk_common * const sg2044_mux_commons[] = {
1583 static struct sg2044_clk_common * const sg2044_gate_commons[] = {
1657 static void sg2044_clk_fix_init_parent(struct clk_hw **pdata,  in sg2044_clk_fix_init_parent()
1675 static int sg2044_clk_init_ctrl(struct device *dev, void __iomem *reg,  in sg2044_clk_init_ctrl()
1759 static int sg2044_clk_probe(struct platform_device *pdev)  in sg2044_clk_probe()
1786 static const struct sg2044_clk_desc_data sg2044_clk_desc_data = {
1795 static const struct of_device_id sg2044_clk_match[] = {
1801 static struct platform_driver sg2044_clk_driver = {