Lines Matching refs:R_RP_RXU_CLK_ENABLE
18 #define R_RP_RXU_CLK_ENABLE (0x0368 - R_SYSGATE_BEGIN) macro
91 0, R_RP_RXU_CLK_ENABLE, 0),
93 0, R_RP_RXU_CLK_ENABLE, 1),
95 0, R_RP_RXU_CLK_ENABLE, 2),
97 0, R_RP_RXU_CLK_ENABLE, 3),
99 0, R_RP_RXU_CLK_ENABLE, 4),
101 0, R_RP_RXU_CLK_ENABLE, 5),
103 0, R_RP_RXU_CLK_ENABLE, 6),
105 0, R_RP_RXU_CLK_ENABLE, 7),
107 0, R_RP_RXU_CLK_ENABLE, 8),
109 0, R_RP_RXU_CLK_ENABLE, 9),
111 0, R_RP_RXU_CLK_ENABLE, 10),
113 0, R_RP_RXU_CLK_ENABLE, 11),
115 0, R_RP_RXU_CLK_ENABLE, 12),
117 0, R_RP_RXU_CLK_ENABLE, 13),
119 0, R_RP_RXU_CLK_ENABLE, 14),
121 0, R_RP_RXU_CLK_ENABLE, 15),
123 0, R_RP_RXU_CLK_ENABLE, 16),
125 0, R_RP_RXU_CLK_ENABLE, 17),
127 0, R_RP_RXU_CLK_ENABLE, 18),
129 0, R_RP_RXU_CLK_ENABLE, 19),
131 0, R_RP_RXU_CLK_ENABLE, 20),
133 0, R_RP_RXU_CLK_ENABLE, 21),
135 0, R_RP_RXU_CLK_ENABLE, 22),
137 0, R_RP_RXU_CLK_ENABLE, 23),
139 0, R_RP_RXU_CLK_ENABLE, 24),
141 0, R_RP_RXU_CLK_ENABLE, 25),
143 0, R_RP_RXU_CLK_ENABLE, 26),
145 0, R_RP_RXU_CLK_ENABLE, 27),
147 0, R_RP_RXU_CLK_ENABLE, 28),
149 0, R_RP_RXU_CLK_ENABLE, 29),
151 0, R_RP_RXU_CLK_ENABLE, 30),
153 0, R_RP_RXU_CLK_ENABLE, 31),