Lines Matching refs:sg2042_div_clks_level_2

573 #define clk_div_top_rp_cmn_div2	(&sg2042_div_clks_level_2[0].hw)
574 #define clk_div_50m_a53		(&sg2042_div_clks_level_2[1].hw)
575 #define clk_div_timer1		(&sg2042_div_clks_level_2[2].hw)
576 #define clk_div_timer2		(&sg2042_div_clks_level_2[3].hw)
577 #define clk_div_timer3		(&sg2042_div_clks_level_2[4].hw)
578 #define clk_div_timer4		(&sg2042_div_clks_level_2[5].hw)
579 #define clk_div_timer5		(&sg2042_div_clks_level_2[6].hw)
580 #define clk_div_timer6		(&sg2042_div_clks_level_2[7].hw)
581 #define clk_div_timer7		(&sg2042_div_clks_level_2[8].hw)
582 #define clk_div_timer8		(&sg2042_div_clks_level_2[9].hw)
583 #define clk_div_uart_500m	(&sg2042_div_clks_level_2[10].hw)
584 #define clk_div_ahb_lpc		(&sg2042_div_clks_level_2[11].hw)
585 #define clk_div_efuse		(&sg2042_div_clks_level_2[12].hw)
586 #define clk_div_tx_eth0		(&sg2042_div_clks_level_2[13].hw)
587 #define clk_div_ptp_ref_i_eth0	(&sg2042_div_clks_level_2[14].hw)
588 #define clk_div_ref_eth0	(&sg2042_div_clks_level_2[15].hw)
589 #define clk_div_emmc		(&sg2042_div_clks_level_2[16].hw)
590 #define clk_div_sd		(&sg2042_div_clks_level_2[17].hw)
591 #define clk_div_top_axi0	(&sg2042_div_clks_level_2[18].hw)
592 #define clk_div_100k_emmc	(&sg2042_div_clks_level_2[19].hw)
593 #define clk_div_100k_sd		(&sg2042_div_clks_level_2[20].hw)
594 #define clk_div_gpio_db		(&sg2042_div_clks_level_2[21].hw)
595 #define clk_div_top_axi_hsperi	(&sg2042_div_clks_level_2[22].hw)
597 static struct sg2042_divider_clock sg2042_div_clks_level_2[] = {  variable
1085 		   ARRAY_SIZE(sg2042_div_clks_level_2) +  in sg2042_clkgen_probe()
1114 	ret = sg2042_clk_register_divs(&pdev->dev, clk_data, sg2042_div_clks_level_2,  in sg2042_clkgen_probe()
1115 				       ARRAY_SIZE(sg2042_div_clks_level_2));  in sg2042_clkgen_probe()