1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include "clk-cv18xx-pll.h"
15 	struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);  in hw_to_cv1800_clk_pll()  local
17 	return container_of(common, struct cv1800_clk_pll, common);  in hw_to_cv1800_clk_pll()
39 	value = readl(pll->common.base + pll->pll_reg);  in ipll_recalc_rate()
58 	for_each_pll_limit_range(pre, &limit->pre_div) {  in ipll_find_rate()
59 		for_each_pll_limit_range(div, &limit->div) {  in ipll_find_rate()
60 			for_each_pll_limit_range(post, &limit->post_div) {  in ipll_find_rate()
66 				if ((trate - tmp) < (trate - best_rate)) {  in ipll_find_rate()
85 	return -EINVAL;  in ipll_find_rate()
93 	return ipll_find_rate(pll->pll_limit, req->best_parent_rate,  in ipll_determine_rate()
94 			      &req->rate, &val);  in ipll_determine_rate()
104 	unsigned long ictrl = 0, mode = 0;  in pll_get_mode_ctrl()  local
107 	for_each_pll_limit_range(mode, &limit->mode) {  in pll_get_mode_ctrl()
108 		for_each_pll_limit_range(ictrl, &limit->ictrl) {  in pll_get_mode_ctrl()
109 			if (mode_ctrl_check(div_sel, ictrl, mode)) {  in pll_get_mode_ctrl()
110 				detected = PLL_SET_SEL_MODE(detected, mode);  in pll_get_mode_ctrl()
121 					  unsigned long mode)  in ipll_check_mode_ctrl_restrict()  argument
125 	unsigned long test = 184 * (1 + mode) * (1 + ictrl) / 2;  in ipll_check_mode_ctrl_restrict()
137 	ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected);  in ipll_set_rate()
140 			  pll->pll_limit, &detected);  in ipll_set_rate()
142 	spin_lock_irqsave(pll->common.lock, flags);  in ipll_set_rate()
144 	regval = readl(pll->common.base + pll->pll_reg);  in ipll_set_rate()
147 	writel(regval, pll->common.base + pll->pll_reg);  in ipll_set_rate()
149 	spin_unlock_irqrestore(pll->common.lock, flags);  in ipll_set_rate()
151 	cv1800_clk_wait_for_lock(&pll->common, pll->pll_status.reg,  in ipll_set_rate()
152 			      BIT(pll->pll_status.shift));  in ipll_set_rate()
161 	return cv1800_clk_clearbit(&pll->common, &pll->pll_pwd);  in pll_enable()
168 	cv1800_clk_setbit(&pll->common, &pll->pll_pwd);  in pll_disable()
175 	return cv1800_clk_checkbit(&pll->common, &pll->pll_pwd) == 0;  in pll_is_enable()
193 	return cv1800_clk_checkbit(&pll->common, &pll->pll_syn->en);  in fpll_is_factional_mode()
207 	dividend <<= PLL_SYN_FACTOR_DOT_POS - 1;  in fpll_calc_rate()
231 	syn_set = readl(pll->common.base + pll->pll_syn->set);  in fpll_recalc_rate()
236 	clk_full = cv1800_clk_checkbit(&pll->common,  in fpll_recalc_rate()
237 					  &pll->pll_syn->clk_half);  in fpll_recalc_rate()
239 	value = readl(pll->common.base + pll->pll_reg);  in fpll_recalc_rate()
273 			test_max = tssc - 1;  in fpll_find_synthesizer()
294 	bool clk_full = cv1800_clk_checkbit(&pll->common,  in fpll_find_rate()
295 					       &pll->pll_syn->clk_half);  in fpll_find_rate()
297 	for_each_pll_limit_range(pre, &limit->pre_div) {  in fpll_find_rate()
298 		for_each_pll_limit_range(post, &limit->post_div) {  in fpll_find_rate()
299 			for_each_pll_limit_range(div, &limit->div) {  in fpll_find_rate()
305 				if ((trate - tmp) < (trate - best_rate)) {  in fpll_find_rate()
324 	return -EINVAL;  in fpll_find_rate()
335 	fpll_find_rate(pll, &pll->pll_limit[2], req->best_parent_rate,  in fpll_determine_rate()
336 		       &req->rate, &val, &ssc_syn_set);  in fpll_determine_rate()
343 					  unsigned long mode)  in fpll_check_mode_ctrl_restrict()  argument
347 	unsigned long test = 184 * (1 + mode) * (1 + ictrl) / 2;  in fpll_check_mode_ctrl_restrict()
363 	fpll_find_rate(pll, &pll->pll_limit[2], parent_rate,  in fpll_set_rate()
367 			  pll->pll_limit, &detected);  in fpll_set_rate()
369 	spin_lock_irqsave(pll->common.lock, flags);  in fpll_set_rate()
371 	writel(detected_ssc, pll->common.base + pll->pll_syn->set);  in fpll_set_rate()
373 	regval = readl(pll->common.base + pll->pll_reg);  in fpll_set_rate()
376 	writel(regval, pll->common.base + pll->pll_reg);  in fpll_set_rate()
378 	spin_unlock_irqrestore(pll->common.lock, flags);  in fpll_set_rate()
380 	cv1800_clk_wait_for_lock(&pll->common, pll->pll_status.reg,  in fpll_set_rate()
381 			      BIT(pll->pll_status.shift));  in fpll_set_rate()
401 		cv1800_clk_setbit(&pll->common, &pll->pll_syn->en);  in fpll_set_parent()
403 		cv1800_clk_clearbit(&pll->common, &pll->pll_syn->en);  in fpll_set_parent()