Lines Matching +full:sg2042 +full:- +full:pll

1 # SPDX-License-Identifier: GPL-2.0
14 	tristate "Sophgo SG2042 PLL clock support"
17 	  This driver supports the PLL clock controller on the
18 	  Sophgo SG2042 SoC. This clock IP uses three oscillators with
20 	  PLL, DDR PLL 0 and DDR PLL 1 respectively.
23 	tristate "Sophgo SG2042 Clock Generator support"
27 	  Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
28 	  because it uses PLL clocks as input.
32 	tristate "Sophgo SG2042 RP subsystem clock controller support"
36 	  controller on the Sophgo SG2042 SoC.
37 	  This clock IP depends on SG2042 Clock Generator because it uses
46 	  SoC. This controller requires mulitple PLL clock as input.
47 	  This clock control provides PLL clocks and common clock function
51 	tristate "Sophgo SG2044 PLL clock controller support"
56 	  This driver supports the PLL clock controller on the Sophgo
58 	  This clock control provides PLL clocks on the SoC.