1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
10 #include <dt-bindings/clock/agilex-clock.h>
12 #include "stratix10-clk.h"
17 	{ .fw_name = "cb-intosc-hs-div2-clk",
18 	  .name = "cb-intosc-hs-div2-clk", },
19 	{ .fw_name = "f2s-free-clk",
20 	  .name = "f2s-free-clk", },
26 	{ .fw_name = "cb-intosc-hs-div2-clk",
27 	  .name = "cb-intosc-hs-div2-clk", },
37 	{ .fw_name = "cb-intosc-hs-div2-clk",
38 	  .name = "cb-intosc-hs-div2-clk", },
39 	{ .fw_name = "f2s-free-clk",
40 	  .name = "f2s-free-clk", },
50 	{ .fw_name = "cb-intosc-hs-div2-clk",
51 	  .name = "cb-intosc-hs-div2-clk", },
52 	{ .fw_name = "f2s-free-clk",
53 	  .name = "f2s-free-clk", },
63 	{ .fw_name = "cb-intosc-hs-div2-clk",
64 	  .name = "cb-intosc-hs-div2-clk", },
65 	{ .fw_name = "f2s-free-clk",
66 	  .name = "f2s-free-clk", },
76 	{ .fw_name = "cb-intosc-hs-div2-clk",
77 	  .name = "cb-intosc-hs-div2-clk", },
78 	{ .fw_name = "f2s-free-clk",
79 	  .name = "f2s-free-clk", },
89 	{ .fw_name = "cb-intosc-hs-div2-clk",
90 	  .name = "cb-intosc-hs-div2-clk", },
91 	{ .fw_name = "f2s-free-clk",
92 	  .name = "f2s-free-clk", },
102 	{ .fw_name = "cb-intosc-hs-div2-clk",
103 	  .name = "cb-intosc-hs-div2-clk", },
104 	{ .fw_name = "f2s-free-clk",
105 	  .name = "f2s-free-clk", },
115 	{ .fw_name = "cb-intosc-hs-div2-clk",
116 	  .name = "cb-intosc-hs-div2-clk", },
117 	{ .fw_name = "f2s-free-clk",
118 	  .name = "f2s-free-clk", },
128 	{ .fw_name = "cb-intosc-hs-div2-clk",
129 	  .name = "cb-intosc-hs-div2-clk", },
130 	{ .fw_name = "f2s-free-clk",
131 	  .name = "f2s-free-clk", },
141 	{ .fw_name = "cb-intosc-hs-div2-clk",
142 	  .name = "cb-intosc-hs-div2-clk", },
143 	{ .fw_name = "f2s-free-clk",
144 	  .name = "f2s-free-clk", },
154 	{ .fw_name = "cb-intosc-hs-div2-clk",
155 	  .name = "cb-intosc-hs-div2-clk", },
156 	{ .fw_name = "f2s-free-clk",
157 	  .name = "f2s-free-clk", },
341 	void __iomem *base = data->base;  in n5x_clk_register_c_perip()
351 		data->clk_data.hws[clks[i].id] = hw_clk;  in n5x_clk_register_c_perip()
360 	void __iomem *base = data->base;  in agilex_clk_register_c_perip()
370 		data->clk_data.hws[clks[i].id] = hw_clk;  in agilex_clk_register_c_perip()
379 	void __iomem *base = data->base;  in agilex_clk_register_cnt_perip()
389 		data->clk_data.hws[clks[i].id] = hw_clk;  in agilex_clk_register_cnt_perip()
399 	void __iomem *base = data->base;  in agilex_clk_register_gate()
409 		data->clk_data.hws[clks[i].id] = hw_clk;  in agilex_clk_register_gate()
419 	void __iomem *base = data->base;  in agilex_clk_register_pll()
429 		data->clk_data.hws[clks[i].id] = hw_clk;  in agilex_clk_register_pll()
439 	void __iomem *base = data->base;  in n5x_clk_register_pll()
449 		data->clk_data.hws[clks[i].id] = hw_clk;  in n5x_clk_register_pll()
457 	struct device_node *np = pdev->dev.of_node;  in agilex_clkmgr_init()
458 	struct device *dev = &pdev->dev;  in agilex_clkmgr_init()
472 		return -ENOMEM;  in agilex_clkmgr_init()
474 	clk_data->clk_data.num = num_clks;  in agilex_clkmgr_init()
475 	clk_data->base = base;  in agilex_clkmgr_init()
478 		clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);  in agilex_clkmgr_init()
491 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);  in agilex_clkmgr_init()
497 	struct device_node *np = pdev->dev.of_node;  in n5x_clkmgr_init()
498 	struct device *dev = &pdev->dev;  in n5x_clkmgr_init()
512 		return -ENOMEM;  in n5x_clkmgr_init()
514 	clk_data->base = base;  in n5x_clkmgr_init()
515 	clk_data->clk_data.num = num_clks;  in n5x_clkmgr_init()
518 		clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);  in n5x_clkmgr_init()
531 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);  in n5x_clkmgr_init()
539 	probe_func = of_device_get_match_data(&pdev->dev);  in agilex_clkmgr_probe()
541 		return -ENODEV;  in agilex_clkmgr_probe()
546 	{ .compatible = "intel,agilex-clkmgr",
548 	{ .compatible = "intel,easic-n5x-clkmgr",
556 		.name	= "agilex-clkmgr",