1 // SPDX-License-Identifier: GPL-2.0
11 #include "sifive-prci.h"
12 #include "fu540-prci.h"
13 #include "fu740-prci.h"
20  * __prci_readl() - read from a PRCI register
34 	return readl_relaxed(pd->va + offs);  in __prci_readl()
39 	writel_relaxed(v, pd->va + offs);  in __prci_writel()
42 /* WRPLL-related private functions */
45  * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
64 	c->divr = v;  in __prci_wrpll_unpack()
68 	c->divf = v;  in __prci_wrpll_unpack()
72 	c->divq = v;  in __prci_wrpll_unpack()
76 	c->range = v;  in __prci_wrpll_unpack()
78 	c->flags &=  in __prci_wrpll_unpack()
82 	c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;  in __prci_wrpll_unpack()
86  * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
104 	r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;  in __prci_wrpll_pack()
105 	r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;  in __prci_wrpll_pack()
106 	r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;  in __prci_wrpll_pack()
107 	r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;  in __prci_wrpll_pack()
116  * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
130 	__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));  in __prci_wrpll_read_cfg0()
134  * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
151 	__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);  in __prci_wrpll_write_cfg0()
153 	memcpy(&pwd->c, c, sizeof(*c));  in __prci_wrpll_write_cfg0()
157  * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
167 	__prci_writel(enable, pwd->cfg1_offs, pd);  in __prci_wrpll_write_cfg1()
181 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_prci_wrpll_recalc_rate()
183 	return wrpll_calc_output_rate(&pwd->c, parent_rate);  in sifive_prci_wrpll_recalc_rate()
191 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_prci_wrpll_round_rate()
194 	memcpy(&c, &pwd->c, sizeof(c));  in sifive_prci_wrpll_round_rate()
205 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_prci_wrpll_set_rate()
206 	struct __prci_data *pd = pc->pd;  in sifive_prci_wrpll_set_rate()
209 	r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);  in sifive_prci_wrpll_set_rate()
213 	if (pwd->enable_bypass)  in sifive_prci_wrpll_set_rate()
214 		pwd->enable_bypass(pd);  in sifive_prci_wrpll_set_rate()
216 	__prci_wrpll_write_cfg0(pd, pwd, &pwd->c);  in sifive_prci_wrpll_set_rate()
218 	udelay(wrpll_calc_max_lock_us(&pwd->c));  in sifive_prci_wrpll_set_rate()
226 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_clk_is_enabled()
227 	struct __prci_data *pd = pc->pd;  in sifive_clk_is_enabled()
230 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_clk_is_enabled()
241 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_prci_clock_enable()
242 	struct __prci_data *pd = pc->pd;  in sifive_prci_clock_enable()
249 	if (pwd->disable_bypass)  in sifive_prci_clock_enable()
250 		pwd->disable_bypass(pd);  in sifive_prci_clock_enable()
258 	struct __prci_wrpll_data *pwd = pc->pwd;  in sifive_prci_clock_disable()
259 	struct __prci_data *pd = pc->pd;  in sifive_prci_clock_disable()
262 	if (pwd->enable_bypass)  in sifive_prci_clock_disable()
263 		pwd->enable_bypass(pd);  in sifive_prci_clock_disable()
265 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_prci_clock_disable()
277 	struct __prci_data *pd = pc->pd;  in sifive_prci_tlclksel_recalc_rate()
294 	struct __prci_data *pd = pc->pd;  in sifive_prci_hfpclkplldiv_recalc_rate()
301  * Core clock mux control
305  * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
306  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
308  * Switch the CORECLK mux to the HFCLK input source; return once complete.
325  * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output
327  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
329  * Switch the CORECLK mux to the COREPLL output clock; return once complete.
346  * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
348  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
350  * Switch the CORECLK mux to the final COREPLL output clock; return once
368  * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to
370  * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
372  * Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete.
389  * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to
391  * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
393  * Switch the COREPLL mux to the COREPLL output clock; return once complete.
410  * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to
412  * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
414  * Switch the HFPCLKPLL mux to the HFCLK input source; return once complete.
431  * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to
433  * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
435  * Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete.
455 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_is_enabled()
469 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_enable()
484 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_disable()
493  * __prci_register_clocks() - register clock controls in the PRCI
495  * @pd: The pointer for PRCI per-device instance data
510 	parent_count = of_clk_get_parent_count(dev->of_node);  in __prci_register_clocks()
514 		return -EINVAL;  in __prci_register_clocks()
518 	for (i = 0; i < desc->num_clks; ++i) {  in __prci_register_clocks()
519 		pic = &(desc->clks[i]);  in __prci_register_clocks()
521 		init.name = pic->name;  in __prci_register_clocks()
522 		init.parent_names = &pic->parent_name;  in __prci_register_clocks()
524 		init.ops = pic->ops;  in __prci_register_clocks()
525 		pic->hw.init = &init;  in __prci_register_clocks()
527 		pic->pd = pd;  in __prci_register_clocks()
529 		if (pic->pwd)  in __prci_register_clocks()
530 			__prci_wrpll_read_cfg0(pd, pic->pwd);  in __prci_register_clocks()
532 		r = devm_clk_hw_register(dev, &pic->hw);  in __prci_register_clocks()
539 		pd->hw_clks.hws[i] = &pic->hw;  in __prci_register_clocks()
542 	pd->hw_clks.num = i;  in __prci_register_clocks()
545 					&pd->hw_clks);  in __prci_register_clocks()
555  * sifive_prci_probe() - initialize prci data and check parent count
562 	struct device *dev = &pdev->dev;  in sifive_prci_probe()
567 	desc = of_device_get_match_data(&pdev->dev);  in sifive_prci_probe()
569 	pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL);  in sifive_prci_probe()
571 		return -ENOMEM;  in sifive_prci_probe()
573 	pd->va = devm_platform_ioremap_resource(pdev, 0);  in sifive_prci_probe()
574 	if (IS_ERR(pd->va))  in sifive_prci_probe()
575 		return PTR_ERR(pd->va);  in sifive_prci_probe()
577 	pd->reset.rcdev.owner = THIS_MODULE;  in sifive_prci_probe()
578 	pd->reset.rcdev.nr_resets = PRCI_RST_NR;  in sifive_prci_probe()
579 	pd->reset.rcdev.ops = &reset_simple_ops;  in sifive_prci_probe()
580 	pd->reset.rcdev.of_node = pdev->dev.of_node;  in sifive_prci_probe()
581 	pd->reset.active_low = true;  in sifive_prci_probe()
582 	pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;  in sifive_prci_probe()
583 	spin_lock_init(&pd->reset.lock);  in sifive_prci_probe()
585 	r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);  in sifive_prci_probe()
602 	{.compatible = "sifive,fu540-c000-prci", .data = &prci_clk_fu540},
603 	{.compatible = "sifive,fu740-c000-prci", .data = &prci_clk_fu740},
610 		.name = "sifive-clk-prci",