Lines Matching +full:pll +full:- +full:in
1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
14 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
25 /* PLL enable control bit offset in @con_reg register */
27 /* PLL lock status bit offset in @con_reg register */
37 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
39 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
42 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
53 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_determine_rate() local
54 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_determine_rate()
57 /* Assuming rate_table is in descending order */ in samsung_pll_determine_rate()
58 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_determine_rate()
59 if (req->rate >= rate_table[i].rate) { in samsung_pll_determine_rate()
60 req->rate = rate_table[i].rate; in samsung_pll_determine_rate()
67 req->rate = rate_table[i - 1].rate; in samsung_pll_determine_rate()
72 /* Wait until the PLL is locked */
73 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, in samsung_pll_lock_wait() argument
88 * register read time was usually in range 0.4...1.5 us, never less than in samsung_pll_lock_wait()
91 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, in samsung_pll_lock_wait()
95 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
102 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
105 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
106 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
107 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
109 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll3xxx_enable()
114 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_disable() local
117 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_disable()
118 tmp &= ~BIT(pll->enable_offs); in samsung_pll3xxx_disable()
119 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_disable()
136 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate() local
140 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()
169 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate() local
173 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()
207 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_recalc_rate() local
211 pll_con = readl_relaxed(pll->con_reg); in samsung_pll35xx_recalc_rate()
230 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
236 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_set_rate() local
241 rate = samsung_get_pll_settings(pll, drate); in samsung_pll35xx_set_rate()
243 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll35xx_set_rate()
245 return -EINVAL; in samsung_pll35xx_set_rate()
248 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
253 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; in samsung_pll35xx_set_rate()
254 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
259 /* Set PLL lock time. */ in samsung_pll35xx_set_rate()
260 if (pll->type == pll_142xx || pll->type == pll_1017x) in samsung_pll35xx_set_rate()
261 writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
262 pll->lock_reg); in samsung_pll35xx_set_rate()
264 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
265 pll->lock_reg); in samsung_pll35xx_set_rate()
267 /* Change PLL PMS values */ in samsung_pll35xx_set_rate()
271 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | in samsung_pll35xx_set_rate()
272 (rate->pdiv << PLL35XX_PDIV_SHIFT) | in samsung_pll35xx_set_rate()
273 (rate->sdiv << PLL35XX_SDIV_SHIFT); in samsung_pll35xx_set_rate()
274 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
276 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll35xx_set_rate()
277 if (tmp & BIT(pll->enable_offs)) in samsung_pll35xx_set_rate()
278 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll35xx_set_rate()
315 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_recalc_rate() local
320 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_recalc_rate()
321 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
343 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in samsung_pll36xx_mpk_change()
344 rate->kdiv != old_kdiv); in samsung_pll36xx_mpk_change()
350 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_set_rate() local
354 rate = samsung_get_pll_settings(pll, drate); in samsung_pll36xx_set_rate()
356 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll36xx_set_rate()
358 return -EINVAL; in samsung_pll36xx_set_rate()
361 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
362 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_set_rate()
367 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
368 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
373 /* Set PLL lock time. */ in samsung_pll36xx_set_rate()
374 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
376 /* Change PLL PMS values */ in samsung_pll36xx_set_rate()
380 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | in samsung_pll36xx_set_rate()
381 (rate->pdiv << PLL36XX_PDIV_SHIFT) | in samsung_pll36xx_set_rate()
382 (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
383 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
386 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; in samsung_pll36xx_set_rate()
387 writel_relaxed(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
389 if (pll_con0 & BIT(pll->enable_offs)) in samsung_pll36xx_set_rate()
390 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll36xx_set_rate()
431 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0822x_recalc_rate() local
435 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_recalc_rate()
437 if (pll->type != pll_1418x && in samsung_pll0822x_recalc_rate()
438 pll->type != pll_0717x && in samsung_pll0822x_recalc_rate()
439 pll->type != pll_0718x) in samsung_pll0822x_recalc_rate()
448 if (pll->type == pll_0516x) in samsung_pll0822x_recalc_rate()
460 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0822x_set_rate() local
463 if (pll->type != pll_1418x) in samsung_pll0822x_set_rate()
469 rate = samsung_get_pll_settings(pll, drate); in samsung_pll0822x_set_rate()
471 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll0822x_set_rate()
473 return -EINVAL; in samsung_pll0822x_set_rate()
476 /* Change PLL PMS values */ in samsung_pll0822x_set_rate()
477 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_set_rate()
481 pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | in samsung_pll0822x_set_rate()
482 (rate->pdiv << PLL0822X_PDIV_SHIFT) | in samsung_pll0822x_set_rate()
483 (rate->sdiv << PLL0822X_SDIV_SHIFT); in samsung_pll0822x_set_rate()
485 /* Set PLL lock time */ in samsung_pll0822x_set_rate()
486 writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR, in samsung_pll0822x_set_rate()
487 pll->lock_reg); in samsung_pll0822x_set_rate()
490 writel_relaxed(pll_con3, pll->con_reg); in samsung_pll0822x_set_rate()
492 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll0822x_set_rate()
493 if (pll_con3 & BIT(pll->enable_offs)) in samsung_pll0822x_set_rate()
494 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll0822x_set_rate()
531 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0831x_recalc_rate() local
536 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_recalc_rate()
537 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_recalc_rate()
554 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0831x_set_rate() local
558 rate = samsung_get_pll_settings(pll, drate); in samsung_pll0831x_set_rate()
560 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll0831x_set_rate()
562 return -EINVAL; in samsung_pll0831x_set_rate()
565 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_set_rate()
566 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_set_rate()
568 /* Change PLL PMSK values */ in samsung_pll0831x_set_rate()
572 pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) | in samsung_pll0831x_set_rate()
573 (rate->pdiv << PLL0831X_PDIV_SHIFT) | in samsung_pll0831x_set_rate()
574 (rate->sdiv << PLL0831X_SDIV_SHIFT); in samsung_pll0831x_set_rate()
577 * kdiv is 16-bit 2's complement (s16), but stored as unsigned int. in samsung_pll0831x_set_rate()
578 * Cast it to u16 to avoid leading 0xffff's in case of negative value. in samsung_pll0831x_set_rate()
580 pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT); in samsung_pll0831x_set_rate()
582 /* Set PLL lock time */ in samsung_pll0831x_set_rate()
583 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg); in samsung_pll0831x_set_rate()
586 writel_relaxed(pll_con3, pll->con_reg); in samsung_pll0831x_set_rate()
587 writel_relaxed(pll_con5, pll->con_reg + 8); in samsung_pll0831x_set_rate()
589 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll0831x_set_rate()
590 if (pll_con3 & BIT(pll->enable_offs)) in samsung_pll0831x_set_rate()
591 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll0831x_set_rate()
629 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_recalc_rate() local
633 pll_con = readl_relaxed(pll->con_reg); in samsung_pll45xx_recalc_rate()
638 if (pll->type == pll_4508) in samsung_pll45xx_recalc_rate()
639 sdiv = sdiv - 1; in samsung_pll45xx_recalc_rate()
656 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll45xx_mp_change()
657 || old_afc != rate->afc); in samsung_pll45xx_mp_change()
663 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_set_rate() local
668 rate = samsung_get_pll_settings(pll, drate); in samsung_pll45xx_set_rate()
670 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll45xx_set_rate()
672 return -EINVAL; in samsung_pll45xx_set_rate()
675 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
676 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
681 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
682 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
687 /* Set PLL PMS values. */ in samsung_pll45xx_set_rate()
691 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
692 (rate->pdiv << PLL45XX_PDIV_SHIFT) | in samsung_pll45xx_set_rate()
693 (rate->sdiv << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
695 /* Set PLL AFC value. */ in samsung_pll45xx_set_rate()
696 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
698 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
700 /* Set PLL lock time. */ in samsung_pll45xx_set_rate()
701 switch (pll->type) { in samsung_pll45xx_set_rate()
703 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
706 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
713 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
714 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
716 /* Wait for PLL lock */ in samsung_pll45xx_set_rate()
717 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); in samsung_pll45xx_set_rate()
762 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_recalc_rate() local
766 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_recalc_rate()
767 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll46xx_recalc_rate()
768 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? in samsung_pll46xx_recalc_rate()
772 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : in samsung_pll46xx_recalc_rate()
775 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; in samsung_pll46xx_recalc_rate()
793 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll46xx_mpk_change()
794 || old_kdiv != rate->kdiv); in samsung_pll46xx_mpk_change()
800 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_set_rate() local
805 rate = samsung_get_pll_settings(pll, drate); in samsung_pll46xx_set_rate()
807 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll46xx_set_rate()
809 return -EINVAL; in samsung_pll46xx_set_rate()
812 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
813 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
818 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; in samsung_pll46xx_set_rate()
819 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
824 /* Set PLL lock time. */ in samsung_pll46xx_set_rate()
825 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; in samsung_pll46xx_set_rate()
827 /* Maximum lock time bitfield is 16-bit. */ in samsung_pll46xx_set_rate()
830 /* Set PLL PMS and VSEL values. */ in samsung_pll46xx_set_rate()
831 if (pll->type == pll_1460x) { in samsung_pll46xx_set_rate()
840 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; in samsung_pll46xx_set_rate()
843 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | in samsung_pll46xx_set_rate()
844 (rate->pdiv << PLL46XX_PDIV_SHIFT) | in samsung_pll46xx_set_rate()
845 (rate->sdiv << PLL46XX_SDIV_SHIFT); in samsung_pll46xx_set_rate()
847 /* Set PLL K, MFR and MRR values. */ in samsung_pll46xx_set_rate()
848 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
852 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | in samsung_pll46xx_set_rate()
853 (rate->mfr << PLL46XX_MFR_SHIFT) | in samsung_pll46xx_set_rate()
854 (rate->mrr << PLL46XX_MRR_SHIFT); in samsung_pll46xx_set_rate()
856 /* Write configuration to PLL */ in samsung_pll46xx_set_rate()
857 writel_relaxed(lock, pll->lock_reg); in samsung_pll46xx_set_rate()
858 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
859 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
861 /* Wait for PLL lock */ in samsung_pll46xx_set_rate()
862 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); in samsung_pll46xx_set_rate()
891 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6552_recalc_rate() local
895 pll_con = readl_relaxed(pll->con_reg); in samsung_pll6552_recalc_rate()
896 if (pll->type == pll_6552_s3c2416) { in samsung_pll6552_recalc_rate()
931 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6553_recalc_rate() local
935 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll6553_recalc_rate()
936 pll_con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll6553_recalc_rate()
969 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550x_recalc_rate() local
973 pll_stat = readl_relaxed(pll->con_reg); in samsung_pll2550x_recalc_rate()
1010 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_recalc_rate() local
1014 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2550xx_recalc_rate()
1038 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_set_rate() local
1043 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2550xx_set_rate()
1045 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2550xx_set_rate()
1047 return -EINVAL; in samsung_pll2550xx_set_rate()
1050 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1052 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { in samsung_pll2550xx_set_rate()
1055 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; in samsung_pll2550xx_set_rate()
1056 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1061 /* Set PLL lock time. */ in samsung_pll2550xx_set_rate()
1062 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll2550xx_set_rate()
1064 /* Change PLL PMS values */ in samsung_pll2550xx_set_rate()
1068 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | in samsung_pll2550xx_set_rate()
1069 (rate->pdiv << PLL2550XX_P_SHIFT) | in samsung_pll2550xx_set_rate()
1070 (rate->sdiv << PLL2550XX_S_SHIFT); in samsung_pll2550xx_set_rate()
1071 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1073 /* Wait for PLL lock */ in samsung_pll2550xx_set_rate()
1074 return samsung_pll_lock_wait(pll, in samsung_pll2550xx_set_rate()
1110 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_recalc_rate() local
1115 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_recalc_rate()
1120 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_recalc_rate()
1133 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_set_rate() local
1138 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650x_set_rate()
1140 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650x_set_rate()
1142 return -EINVAL; in samsung_pll2650x_set_rate()
1145 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1146 con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_set_rate()
1148 /* Set PLL lock time. */ in samsung_pll2650x_set_rate()
1149 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); in samsung_pll2650x_set_rate()
1151 /* Change PLL PMS values */ in samsung_pll2650x_set_rate()
1155 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | in samsung_pll2650x_set_rate()
1156 (rate->pdiv << PLL2650X_P_SHIFT) | in samsung_pll2650x_set_rate()
1157 (rate->sdiv << PLL2650X_S_SHIFT); in samsung_pll2650x_set_rate()
1159 writel_relaxed(con0, pll->con_reg); in samsung_pll2650x_set_rate()
1162 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); in samsung_pll2650x_set_rate()
1163 writel_relaxed(con1, pll->con_reg + 4); in samsung_pll2650x_set_rate()
1165 /* Wait for PLL lock */ in samsung_pll2650x_set_rate()
1166 return samsung_pll_lock_wait(pll, in samsung_pll2650x_set_rate()
1202 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_recalc_rate() local
1207 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_recalc_rate()
1208 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_recalc_rate()
1224 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_set_rate() local
1228 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650xx_set_rate()
1230 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650xx_set_rate()
1232 return -EINVAL; in samsung_pll2650xx_set_rate()
1235 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1236 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1238 /* Change PLL PMS values */ in samsung_pll2650xx_set_rate()
1242 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; in samsung_pll2650xx_set_rate()
1243 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; in samsung_pll2650xx_set_rate()
1244 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; in samsung_pll2650xx_set_rate()
1249 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) in samsung_pll2650xx_set_rate()
1252 /* Set PLL lock time. */ in samsung_pll2650xx_set_rate()
1253 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); in samsung_pll2650xx_set_rate()
1255 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll2650xx_set_rate()
1256 writel_relaxed(pll_con2, pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1258 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); in samsung_pll2650xx_set_rate()
1287 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll531x_recalc_rate() local
1291 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll531x_recalc_rate()
1292 pll_con8 = readl_relaxed(pll->con_reg + 20); in samsung_pll531x_recalc_rate()
1299 mdiv--; in samsung_pll531x_recalc_rate()
1334 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll1031x_recalc_rate() local
1338 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll1031x_recalc_rate()
1339 pll_con3 = readl_relaxed(pll->con_reg + 0xc); in samsung_pll1031x_recalc_rate()
1361 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv || in samsung_pll1031x_mpk_change()
1362 old_kdiv != rate->kdiv); in samsung_pll1031x_mpk_change()
1368 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll1031x_set_rate() local
1373 rate = samsung_get_pll_settings(pll, drate); in samsung_pll1031x_set_rate()
1375 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll1031x_set_rate()
1377 return -EINVAL; in samsung_pll1031x_set_rate()
1380 con0 = readl_relaxed(pll->con_reg); in samsung_pll1031x_set_rate()
1381 con3 = readl_relaxed(pll->con_reg + 0xc); in samsung_pll1031x_set_rate()
1386 con0 |= rate->sdiv << PLL1031X_SDIV_SHIFT; in samsung_pll1031x_set_rate()
1387 writel_relaxed(con0, pll->con_reg); in samsung_pll1031x_set_rate()
1392 /* Set PLL lock time. */ in samsung_pll1031x_set_rate()
1393 writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg); in samsung_pll1031x_set_rate()
1395 /* Set PLL M, P, and S values. */ in samsung_pll1031x_set_rate()
1400 con0 |= (rate->mdiv << PLL1031X_MDIV_SHIFT) | in samsung_pll1031x_set_rate()
1401 (rate->pdiv << PLL1031X_PDIV_SHIFT) | in samsung_pll1031x_set_rate()
1402 (rate->sdiv << PLL1031X_SDIV_SHIFT); in samsung_pll1031x_set_rate()
1404 /* Set PLL K, MFR and MRR values. */ in samsung_pll1031x_set_rate()
1405 con3 = readl_relaxed(pll->con_reg + 0xc); in samsung_pll1031x_set_rate()
1409 con3 |= (rate->kdiv << PLL1031X_KDIV_SHIFT) | in samsung_pll1031x_set_rate()
1410 (rate->mfr << PLL1031X_MFR_SHIFT) | in samsung_pll1031x_set_rate()
1411 (rate->mrr << PLL1031X_MRR_SHIFT); in samsung_pll1031x_set_rate()
1413 /* Write configuration to PLL */ in samsung_pll1031x_set_rate()
1414 writel_relaxed(con0, pll->con_reg); in samsung_pll1031x_set_rate()
1415 writel_relaxed(con3, pll->con_reg + 0xc); in samsung_pll1031x_set_rate()
1417 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll1031x_set_rate()
1418 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll1031x_set_rate()
1434 struct samsung_clk_pll *pll; in _samsung_clk_register_pll() local
1438 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _samsung_clk_register_pll()
1439 if (!pll) { in _samsung_clk_register_pll()
1440 pr_err("%s: could not allocate pll clk %s\n", in _samsung_clk_register_pll()
1441 __func__, pll_clk->name); in _samsung_clk_register_pll()
1445 init.name = pll_clk->name; in _samsung_clk_register_pll()
1446 init.flags = pll_clk->flags; in _samsung_clk_register_pll()
1447 init.parent_names = &pll_clk->parent_name; in _samsung_clk_register_pll()
1450 if (pll_clk->rate_table) { in _samsung_clk_register_pll()
1451 /* find count of rates in rate_table */ in _samsung_clk_register_pll()
1452 for (len = 0; pll_clk->rate_table[len].rate != 0; ) in _samsung_clk_register_pll()
1455 pll->rate_count = len; in _samsung_clk_register_pll()
1456 pll->rate_table = kmemdup_array(pll_clk->rate_table, in _samsung_clk_register_pll()
1457 pll->rate_count, in _samsung_clk_register_pll()
1458 sizeof(*pll->rate_table), in _samsung_clk_register_pll()
1460 WARN(!pll->rate_table, in _samsung_clk_register_pll()
1462 __func__, pll_clk->name); in _samsung_clk_register_pll()
1465 switch (pll_clk->type) { in _samsung_clk_register_pll()
1480 pll->enable_offs = PLL35XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1481 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1482 if (!pll->rate_table) in _samsung_clk_register_pll()
1499 pll->enable_offs = PLL0822X_ENABLE_SHIFT; in _samsung_clk_register_pll()
1500 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1501 if (!pll->rate_table) in _samsung_clk_register_pll()
1511 if (!pll->rate_table) in _samsung_clk_register_pll()
1519 pll->enable_offs = PLL36XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1520 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1521 if (!pll->rate_table) in _samsung_clk_register_pll()
1527 pll->enable_offs = PLL0831X_ENABLE_SHIFT; in _samsung_clk_register_pll()
1528 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1529 if (!pll->rate_table) in _samsung_clk_register_pll()
1545 if (!pll->rate_table) in _samsung_clk_register_pll()
1554 if (!pll->rate_table) in _samsung_clk_register_pll()
1560 if (!pll->rate_table) in _samsung_clk_register_pll()
1566 if (!pll->rate_table) in _samsung_clk_register_pll()
1576 if (!pll->rate_table) in _samsung_clk_register_pll()
1582 pr_warn("%s: Unknown pll type for pll clk %s\n", in _samsung_clk_register_pll()
1583 __func__, pll_clk->name); in _samsung_clk_register_pll()
1586 pll->hw.init = &init; in _samsung_clk_register_pll()
1587 pll->type = pll_clk->type; in _samsung_clk_register_pll()
1588 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset; in _samsung_clk_register_pll()
1589 pll->con_reg = ctx->reg_base + pll_clk->con_offset; in _samsung_clk_register_pll()
1591 ret = clk_hw_register(ctx->dev, &pll->hw); in _samsung_clk_register_pll()
1593 pr_err("%s: failed to register pll clock %s : %d\n", in _samsung_clk_register_pll()
1594 __func__, pll_clk->name, ret); in _samsung_clk_register_pll()
1595 kfree(pll->rate_table); in _samsung_clk_register_pll()
1596 kfree(pll); in _samsung_clk_register_pll()
1600 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); in _samsung_clk_register_pll()