Lines Matching +full:pll +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
15 #include <linux/clk-provider.h>
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
60 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
66 return rate_table[i - 1].rate; in samsung_pll_round_rate()
78 /* Wait until the PLL is locked */
79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, in samsung_pll_lock_wait() argument
98 while (i-- > 0) { in samsung_pll_lock_wait()
99 if (readl_relaxed(pll->con_reg) & reg_mask) in samsung_pll_lock_wait()
104 ret = -ETIMEDOUT; in samsung_pll_lock_wait()
106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, in samsung_pll_lock_wait()
111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
118 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_enable() local
121 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_enable()
122 tmp |= BIT(pll->enable_offs); in samsung_pll3xxx_enable()
123 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_enable()
125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll3xxx_enable()
130 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3xxx_disable() local
133 tmp = readl_relaxed(pll->con_reg); in samsung_pll3xxx_disable()
134 tmp &= ~BIT(pll->enable_offs); in samsung_pll3xxx_disable()
135 writel_relaxed(tmp, pll->con_reg); in samsung_pll3xxx_disable()
152 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate() local
156 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2126_recalc_rate()
185 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate() local
189 pll_con = readl_relaxed(pll->con_reg); in samsung_pll3000_recalc_rate()
223 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_recalc_rate() local
227 pll_con = readl_relaxed(pll->con_reg); in samsung_pll35xx_recalc_rate()
246 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
252 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll35xx_set_rate() local
257 rate = samsung_get_pll_settings(pll, drate); in samsung_pll35xx_set_rate()
259 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll35xx_set_rate()
261 return -EINVAL; in samsung_pll35xx_set_rate()
264 tmp = readl_relaxed(pll->con_reg); in samsung_pll35xx_set_rate()
269 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; in samsung_pll35xx_set_rate()
270 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
275 /* Set PLL lock time. */ in samsung_pll35xx_set_rate()
276 if (pll->type == pll_142xx) in samsung_pll35xx_set_rate()
277 writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
278 pll->lock_reg); in samsung_pll35xx_set_rate()
280 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
281 pll->lock_reg); in samsung_pll35xx_set_rate()
283 /* Change PLL PMS values */ in samsung_pll35xx_set_rate()
287 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | in samsung_pll35xx_set_rate()
288 (rate->pdiv << PLL35XX_PDIV_SHIFT) | in samsung_pll35xx_set_rate()
289 (rate->sdiv << PLL35XX_SDIV_SHIFT); in samsung_pll35xx_set_rate()
290 writel_relaxed(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
292 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll35xx_set_rate()
293 if (tmp & BIT(pll->enable_offs)) in samsung_pll35xx_set_rate()
294 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll35xx_set_rate()
331 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_recalc_rate() local
336 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_recalc_rate()
337 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
359 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || in samsung_pll36xx_mpk_change()
360 rate->kdiv != old_kdiv); in samsung_pll36xx_mpk_change()
366 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll36xx_set_rate() local
370 rate = samsung_get_pll_settings(pll, drate); in samsung_pll36xx_set_rate()
372 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll36xx_set_rate()
374 return -EINVAL; in samsung_pll36xx_set_rate()
377 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll36xx_set_rate()
378 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll36xx_set_rate()
383 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
384 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
389 /* Set PLL lock time. */ in samsung_pll36xx_set_rate()
390 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
392 /* Change PLL PMS values */ in samsung_pll36xx_set_rate()
396 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | in samsung_pll36xx_set_rate()
397 (rate->pdiv << PLL36XX_PDIV_SHIFT) | in samsung_pll36xx_set_rate()
398 (rate->sdiv << PLL36XX_SDIV_SHIFT); in samsung_pll36xx_set_rate()
399 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
402 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; in samsung_pll36xx_set_rate()
403 writel_relaxed(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
405 if (pll_con0 & BIT(pll->enable_offs)) in samsung_pll36xx_set_rate()
406 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll36xx_set_rate()
447 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0822x_recalc_rate() local
451 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_recalc_rate()
453 if (pll->type != pll_1418x && in samsung_pll0822x_recalc_rate()
454 pll->type != pll_0717x && in samsung_pll0822x_recalc_rate()
455 pll->type != pll_0718x) in samsung_pll0822x_recalc_rate()
464 if (pll->type == pll_0516x) in samsung_pll0822x_recalc_rate()
476 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0822x_set_rate() local
479 if (pll->type != pll_1418x) in samsung_pll0822x_set_rate()
485 rate = samsung_get_pll_settings(pll, drate); in samsung_pll0822x_set_rate()
487 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll0822x_set_rate()
489 return -EINVAL; in samsung_pll0822x_set_rate()
492 /* Change PLL PMS values */ in samsung_pll0822x_set_rate()
493 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0822x_set_rate()
497 pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | in samsung_pll0822x_set_rate()
498 (rate->pdiv << PLL0822X_PDIV_SHIFT) | in samsung_pll0822x_set_rate()
499 (rate->sdiv << PLL0822X_SDIV_SHIFT); in samsung_pll0822x_set_rate()
501 /* Set PLL lock time */ in samsung_pll0822x_set_rate()
502 writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR, in samsung_pll0822x_set_rate()
503 pll->lock_reg); in samsung_pll0822x_set_rate()
506 writel_relaxed(pll_con3, pll->con_reg); in samsung_pll0822x_set_rate()
508 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll0822x_set_rate()
509 if (pll_con3 & BIT(pll->enable_offs)) in samsung_pll0822x_set_rate()
510 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll0822x_set_rate()
547 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0831x_recalc_rate() local
552 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_recalc_rate()
553 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_recalc_rate()
570 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll0831x_set_rate() local
574 rate = samsung_get_pll_settings(pll, drate); in samsung_pll0831x_set_rate()
576 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll0831x_set_rate()
578 return -EINVAL; in samsung_pll0831x_set_rate()
581 pll_con3 = readl_relaxed(pll->con_reg); in samsung_pll0831x_set_rate()
582 pll_con5 = readl_relaxed(pll->con_reg + 8); in samsung_pll0831x_set_rate()
584 /* Change PLL PMSK values */ in samsung_pll0831x_set_rate()
588 pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) | in samsung_pll0831x_set_rate()
589 (rate->pdiv << PLL0831X_PDIV_SHIFT) | in samsung_pll0831x_set_rate()
590 (rate->sdiv << PLL0831X_SDIV_SHIFT); in samsung_pll0831x_set_rate()
593 * kdiv is 16-bit 2's complement (s16), but stored as unsigned int. in samsung_pll0831x_set_rate()
596 pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT); in samsung_pll0831x_set_rate()
598 /* Set PLL lock time */ in samsung_pll0831x_set_rate()
599 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg); in samsung_pll0831x_set_rate()
602 writel_relaxed(pll_con3, pll->con_reg); in samsung_pll0831x_set_rate()
603 writel_relaxed(pll_con5, pll->con_reg + 8); in samsung_pll0831x_set_rate()
605 /* Wait for PLL lock if the PLL is enabled */ in samsung_pll0831x_set_rate()
606 if (pll_con3 & BIT(pll->enable_offs)) in samsung_pll0831x_set_rate()
607 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); in samsung_pll0831x_set_rate()
645 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_recalc_rate() local
649 pll_con = readl_relaxed(pll->con_reg); in samsung_pll45xx_recalc_rate()
654 if (pll->type == pll_4508) in samsung_pll45xx_recalc_rate()
655 sdiv = sdiv - 1; in samsung_pll45xx_recalc_rate()
672 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll45xx_mp_change()
673 || old_afc != rate->afc); in samsung_pll45xx_mp_change()
679 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll45xx_set_rate() local
684 rate = samsung_get_pll_settings(pll, drate); in samsung_pll45xx_set_rate()
686 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll45xx_set_rate()
688 return -EINVAL; in samsung_pll45xx_set_rate()
691 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
692 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
697 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
698 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
703 /* Set PLL PMS values. */ in samsung_pll45xx_set_rate()
707 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
708 (rate->pdiv << PLL45XX_PDIV_SHIFT) | in samsung_pll45xx_set_rate()
709 (rate->sdiv << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
711 /* Set PLL AFC value. */ in samsung_pll45xx_set_rate()
712 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
714 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
716 /* Set PLL lock time. */ in samsung_pll45xx_set_rate()
717 switch (pll->type) { in samsung_pll45xx_set_rate()
719 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
722 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
729 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
730 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
732 /* Wait for PLL lock */ in samsung_pll45xx_set_rate()
733 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); in samsung_pll45xx_set_rate()
778 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_recalc_rate() local
782 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_recalc_rate()
783 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll46xx_recalc_rate()
784 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? in samsung_pll46xx_recalc_rate()
788 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : in samsung_pll46xx_recalc_rate()
791 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; in samsung_pll46xx_recalc_rate()
809 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv in samsung_pll46xx_mpk_change()
810 || old_kdiv != rate->kdiv); in samsung_pll46xx_mpk_change()
816 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll46xx_set_rate() local
821 rate = samsung_get_pll_settings(pll, drate); in samsung_pll46xx_set_rate()
823 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll46xx_set_rate()
825 return -EINVAL; in samsung_pll46xx_set_rate()
828 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
829 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
834 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; in samsung_pll46xx_set_rate()
835 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
840 /* Set PLL lock time. */ in samsung_pll46xx_set_rate()
841 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; in samsung_pll46xx_set_rate()
843 /* Maximum lock time bitfield is 16-bit. */ in samsung_pll46xx_set_rate()
846 /* Set PLL PMS and VSEL values. */ in samsung_pll46xx_set_rate()
847 if (pll->type == pll_1460x) { in samsung_pll46xx_set_rate()
856 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; in samsung_pll46xx_set_rate()
859 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | in samsung_pll46xx_set_rate()
860 (rate->pdiv << PLL46XX_PDIV_SHIFT) | in samsung_pll46xx_set_rate()
861 (rate->sdiv << PLL46XX_SDIV_SHIFT); in samsung_pll46xx_set_rate()
863 /* Set PLL K, MFR and MRR values. */ in samsung_pll46xx_set_rate()
864 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
868 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | in samsung_pll46xx_set_rate()
869 (rate->mfr << PLL46XX_MFR_SHIFT) | in samsung_pll46xx_set_rate()
870 (rate->mrr << PLL46XX_MRR_SHIFT); in samsung_pll46xx_set_rate()
872 /* Write configuration to PLL */ in samsung_pll46xx_set_rate()
873 writel_relaxed(lock, pll->lock_reg); in samsung_pll46xx_set_rate()
874 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
875 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
877 /* Wait for PLL lock */ in samsung_pll46xx_set_rate()
878 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); in samsung_pll46xx_set_rate()
907 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6552_recalc_rate() local
911 pll_con = readl_relaxed(pll->con_reg); in samsung_pll6552_recalc_rate()
912 if (pll->type == pll_6552_s3c2416) { in samsung_pll6552_recalc_rate()
947 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll6553_recalc_rate() local
951 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll6553_recalc_rate()
952 pll_con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll6553_recalc_rate()
985 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550x_recalc_rate() local
989 pll_stat = readl_relaxed(pll->con_reg); in samsung_pll2550x_recalc_rate()
1026 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_recalc_rate() local
1030 pll_con = readl_relaxed(pll->con_reg); in samsung_pll2550xx_recalc_rate()
1054 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2550xx_set_rate() local
1059 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2550xx_set_rate()
1061 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2550xx_set_rate()
1063 return -EINVAL; in samsung_pll2550xx_set_rate()
1066 tmp = readl_relaxed(pll->con_reg); in samsung_pll2550xx_set_rate()
1068 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { in samsung_pll2550xx_set_rate()
1071 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; in samsung_pll2550xx_set_rate()
1072 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1077 /* Set PLL lock time. */ in samsung_pll2550xx_set_rate()
1078 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll2550xx_set_rate()
1080 /* Change PLL PMS values */ in samsung_pll2550xx_set_rate()
1084 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | in samsung_pll2550xx_set_rate()
1085 (rate->pdiv << PLL2550XX_P_SHIFT) | in samsung_pll2550xx_set_rate()
1086 (rate->sdiv << PLL2550XX_S_SHIFT); in samsung_pll2550xx_set_rate()
1087 writel_relaxed(tmp, pll->con_reg); in samsung_pll2550xx_set_rate()
1089 /* Wait for PLL lock */ in samsung_pll2550xx_set_rate()
1090 return samsung_pll_lock_wait(pll, in samsung_pll2550xx_set_rate()
1126 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_recalc_rate() local
1131 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_recalc_rate()
1136 pll_con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_recalc_rate()
1149 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650x_set_rate() local
1154 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650x_set_rate()
1156 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650x_set_rate()
1158 return -EINVAL; in samsung_pll2650x_set_rate()
1161 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
1162 con1 = readl_relaxed(pll->con_reg + 4); in samsung_pll2650x_set_rate()
1164 /* Set PLL lock time. */ in samsung_pll2650x_set_rate()
1165 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); in samsung_pll2650x_set_rate()
1167 /* Change PLL PMS values */ in samsung_pll2650x_set_rate()
1171 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | in samsung_pll2650x_set_rate()
1172 (rate->pdiv << PLL2650X_P_SHIFT) | in samsung_pll2650x_set_rate()
1173 (rate->sdiv << PLL2650X_S_SHIFT); in samsung_pll2650x_set_rate()
1175 writel_relaxed(con0, pll->con_reg); in samsung_pll2650x_set_rate()
1178 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); in samsung_pll2650x_set_rate()
1179 writel_relaxed(con1, pll->con_reg + 4); in samsung_pll2650x_set_rate()
1181 /* Wait for PLL lock */ in samsung_pll2650x_set_rate()
1182 return samsung_pll_lock_wait(pll, in samsung_pll2650x_set_rate()
1218 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_recalc_rate() local
1223 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_recalc_rate()
1224 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_recalc_rate()
1240 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2650xx_set_rate() local
1244 rate = samsung_get_pll_settings(pll, drate); in samsung_pll2650xx_set_rate()
1246 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in samsung_pll2650xx_set_rate()
1248 return -EINVAL; in samsung_pll2650xx_set_rate()
1251 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll2650xx_set_rate()
1252 pll_con2 = readl_relaxed(pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1254 /* Change PLL PMS values */ in samsung_pll2650xx_set_rate()
1258 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; in samsung_pll2650xx_set_rate()
1259 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; in samsung_pll2650xx_set_rate()
1260 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; in samsung_pll2650xx_set_rate()
1265 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) in samsung_pll2650xx_set_rate()
1268 /* Set PLL lock time. */ in samsung_pll2650xx_set_rate()
1269 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); in samsung_pll2650xx_set_rate()
1271 writel_relaxed(pll_con0, pll->con_reg); in samsung_pll2650xx_set_rate()
1272 writel_relaxed(pll_con2, pll->con_reg + 8); in samsung_pll2650xx_set_rate()
1274 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); in samsung_pll2650xx_set_rate()
1303 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll531x_recalc_rate() local
1307 pll_con0 = readl_relaxed(pll->con_reg); in samsung_pll531x_recalc_rate()
1308 pll_con8 = readl_relaxed(pll->con_reg + 20); in samsung_pll531x_recalc_rate()
1315 mdiv--; in samsung_pll531x_recalc_rate()
1331 struct samsung_clk_pll *pll; in _samsung_clk_register_pll() local
1335 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in _samsung_clk_register_pll()
1336 if (!pll) { in _samsung_clk_register_pll()
1337 pr_err("%s: could not allocate pll clk %s\n", in _samsung_clk_register_pll()
1338 __func__, pll_clk->name); in _samsung_clk_register_pll()
1342 init.name = pll_clk->name; in _samsung_clk_register_pll()
1343 init.flags = pll_clk->flags; in _samsung_clk_register_pll()
1344 init.parent_names = &pll_clk->parent_name; in _samsung_clk_register_pll()
1347 if (pll_clk->rate_table) { in _samsung_clk_register_pll()
1349 for (len = 0; pll_clk->rate_table[len].rate != 0; ) in _samsung_clk_register_pll()
1352 pll->rate_count = len; in _samsung_clk_register_pll()
1353 pll->rate_table = kmemdup_array(pll_clk->rate_table, in _samsung_clk_register_pll()
1354 pll->rate_count, in _samsung_clk_register_pll()
1355 sizeof(*pll->rate_table), in _samsung_clk_register_pll()
1357 WARN(!pll->rate_table, in _samsung_clk_register_pll()
1359 __func__, pll_clk->name); in _samsung_clk_register_pll()
1362 switch (pll_clk->type) { in _samsung_clk_register_pll()
1376 pll->enable_offs = PLL35XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1377 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1378 if (!pll->rate_table) in _samsung_clk_register_pll()
1395 pll->enable_offs = PLL0822X_ENABLE_SHIFT; in _samsung_clk_register_pll()
1396 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1397 if (!pll->rate_table) in _samsung_clk_register_pll()
1407 if (!pll->rate_table) in _samsung_clk_register_pll()
1415 pll->enable_offs = PLL36XX_ENABLE_SHIFT; in _samsung_clk_register_pll()
1416 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1417 if (!pll->rate_table) in _samsung_clk_register_pll()
1423 pll->enable_offs = PLL0831X_ENABLE_SHIFT; in _samsung_clk_register_pll()
1424 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; in _samsung_clk_register_pll()
1425 if (!pll->rate_table) in _samsung_clk_register_pll()
1441 if (!pll->rate_table) in _samsung_clk_register_pll()
1450 if (!pll->rate_table) in _samsung_clk_register_pll()
1456 if (!pll->rate_table) in _samsung_clk_register_pll()
1462 if (!pll->rate_table) in _samsung_clk_register_pll()
1471 pr_warn("%s: Unknown pll type for pll clk %s\n", in _samsung_clk_register_pll()
1472 __func__, pll_clk->name); in _samsung_clk_register_pll()
1475 pll->hw.init = &init; in _samsung_clk_register_pll()
1476 pll->type = pll_clk->type; in _samsung_clk_register_pll()
1477 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset; in _samsung_clk_register_pll()
1478 pll->con_reg = ctx->reg_base + pll_clk->con_offset; in _samsung_clk_register_pll()
1480 ret = clk_hw_register(ctx->dev, &pll->hw); in _samsung_clk_register_pll()
1482 pr_err("%s: failed to register pll clock %s : %d\n", in _samsung_clk_register_pll()
1483 __func__, pll_clk->name, ret); in _samsung_clk_register_pll()
1484 kfree(pll->rate_table); in _samsung_clk_register_pll()
1485 kfree(pll); in _samsung_clk_register_pll()
1489 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); in _samsung_clk_register_pll()