Lines Matching defs:pll
6 * This file contains the utility functions to register the pll clocks.
18 #include "clk-pll.h"
39 struct samsung_clk_pll *pll, unsigned long rate)
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
44 for (i = 0; i < pll->rate_count; i++) {
55 struct samsung_clk_pll *pll = to_clk_pll(hw);
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
60 for (i = 0; i < pll->rate_count; i++) {
79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
99 if (readl_relaxed(pll->con_reg) & reg_mask)
106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));
118 struct samsung_clk_pll *pll = to_clk_pll(hw);
121 tmp = readl_relaxed(pll->con_reg);
122 tmp |= BIT(pll->enable_offs);
123 writel_relaxed(tmp, pll->con_reg);
125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
130 struct samsung_clk_pll *pll = to_clk_pll(hw);
133 tmp = readl_relaxed(pll->con_reg);
134 tmp &= ~BIT(pll->enable_offs);
135 writel_relaxed(tmp, pll->con_reg);
152 struct samsung_clk_pll *pll = to_clk_pll(hw);
156 pll_con = readl_relaxed(pll->con_reg);
185 struct samsung_clk_pll *pll = to_clk_pll(hw);
189 pll_con = readl_relaxed(pll->con_reg);
223 struct samsung_clk_pll *pll = to_clk_pll(hw);
227 pll_con = readl_relaxed(pll->con_reg);
252 struct samsung_clk_pll *pll = to_clk_pll(hw);
257 rate = samsung_get_pll_settings(pll, drate);
259 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
264 tmp = readl_relaxed(pll->con_reg);
270 writel_relaxed(tmp, pll->con_reg);
276 if (pll->type == pll_142xx)
278 pll->lock_reg);
281 pll->lock_reg);
290 writel_relaxed(tmp, pll->con_reg);
293 if (tmp & BIT(pll->enable_offs))
294 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
331 struct samsung_clk_pll *pll = to_clk_pll(hw);
336 pll_con0 = readl_relaxed(pll->con_reg);
337 pll_con1 = readl_relaxed(pll->con_reg + 4);
366 struct samsung_clk_pll *pll = to_clk_pll(hw);
370 rate = samsung_get_pll_settings(pll, drate);
372 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
377 pll_con0 = readl_relaxed(pll->con_reg);
378 pll_con1 = readl_relaxed(pll->con_reg + 4);
384 writel_relaxed(pll_con0, pll->con_reg);
390 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
399 writel_relaxed(pll_con0, pll->con_reg);
403 writel_relaxed(pll_con1, pll->con_reg + 4);
405 if (pll_con0 & BIT(pll->enable_offs))
406 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
447 struct samsung_clk_pll *pll = to_clk_pll(hw);
451 pll_con3 = readl_relaxed(pll->con_reg);
453 if (pll->type != pll_1418x &&
454 pll->type != pll_0717x &&
455 pll->type != pll_0718x)
464 if (pll->type == pll_0516x)
476 struct samsung_clk_pll *pll = to_clk_pll(hw);
479 if (pll->type != pll_1418x)
485 rate = samsung_get_pll_settings(pll, drate);
487 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
493 pll_con3 = readl_relaxed(pll->con_reg);
503 pll->lock_reg);
506 writel_relaxed(pll_con3, pll->con_reg);
509 if (pll_con3 & BIT(pll->enable_offs))
510 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
547 struct samsung_clk_pll *pll = to_clk_pll(hw);
552 pll_con3 = readl_relaxed(pll->con_reg);
553 pll_con5 = readl_relaxed(pll->con_reg + 8);
570 struct samsung_clk_pll *pll = to_clk_pll(hw);
574 rate = samsung_get_pll_settings(pll, drate);
576 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
581 pll_con3 = readl_relaxed(pll->con_reg);
582 pll_con5 = readl_relaxed(pll->con_reg + 8);
599 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg);
602 writel_relaxed(pll_con3, pll->con_reg);
603 writel_relaxed(pll_con5, pll->con_reg + 8);
606 if (pll_con3 & BIT(pll->enable_offs))
607 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
645 struct samsung_clk_pll *pll = to_clk_pll(hw);
649 pll_con = readl_relaxed(pll->con_reg);
654 if (pll->type == pll_4508)
679 struct samsung_clk_pll *pll = to_clk_pll(hw);
684 rate = samsung_get_pll_settings(pll, drate);
686 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
691 con0 = readl_relaxed(pll->con_reg);
692 con1 = readl_relaxed(pll->con_reg + 0x4);
698 writel_relaxed(con0, pll->con_reg);
712 con1 = readl_relaxed(pll->con_reg + 0x4);
717 switch (pll->type) {
719 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
722 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
729 writel_relaxed(con1, pll->con_reg + 0x4);
730 writel_relaxed(con0, pll->con_reg);
733 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED);
778 struct samsung_clk_pll *pll = to_clk_pll(hw);
782 pll_con0 = readl_relaxed(pll->con_reg);
783 pll_con1 = readl_relaxed(pll->con_reg + 4);
784 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
788 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
791 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
816 struct samsung_clk_pll *pll = to_clk_pll(hw);
821 rate = samsung_get_pll_settings(pll, drate);
823 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
828 con0 = readl_relaxed(pll->con_reg);
829 con1 = readl_relaxed(pll->con_reg + 0x4);
835 writel_relaxed(con0, pll->con_reg);
847 if (pll->type == pll_1460x) {
864 con1 = readl_relaxed(pll->con_reg + 0x4);
873 writel_relaxed(lock, pll->lock_reg);
874 writel_relaxed(con0, pll->con_reg);
875 writel_relaxed(con1, pll->con_reg + 0x4);
878 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED);
907 struct samsung_clk_pll *pll = to_clk_pll(hw);
911 pll_con = readl_relaxed(pll->con_reg);
912 if (pll->type == pll_6552_s3c2416) {
947 struct samsung_clk_pll *pll = to_clk_pll(hw);
951 pll_con0 = readl_relaxed(pll->con_reg);
952 pll_con1 = readl_relaxed(pll->con_reg + 0x4);
985 struct samsung_clk_pll *pll = to_clk_pll(hw);
989 pll_stat = readl_relaxed(pll->con_reg);
1026 struct samsung_clk_pll *pll = to_clk_pll(hw);
1030 pll_con = readl_relaxed(pll->con_reg);
1054 struct samsung_clk_pll *pll = to_clk_pll(hw);
1059 rate = samsung_get_pll_settings(pll, drate);
1061 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1066 tmp = readl_relaxed(pll->con_reg);
1072 writel_relaxed(tmp, pll->con_reg);
1078 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
1087 writel_relaxed(tmp, pll->con_reg);
1090 return samsung_pll_lock_wait(pll,
1126 struct samsung_clk_pll *pll = to_clk_pll(hw);
1131 pll_con0 = readl_relaxed(pll->con_reg);
1136 pll_con1 = readl_relaxed(pll->con_reg + 4);
1149 struct samsung_clk_pll *pll = to_clk_pll(hw);
1154 rate = samsung_get_pll_settings(pll, drate);
1156 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1161 con0 = readl_relaxed(pll->con_reg);
1162 con1 = readl_relaxed(pll->con_reg + 4);
1165 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
1175 writel_relaxed(con0, pll->con_reg);
1179 writel_relaxed(con1, pll->con_reg + 4);
1182 return samsung_pll_lock_wait(pll,
1218 struct samsung_clk_pll *pll = to_clk_pll(hw);
1223 pll_con0 = readl_relaxed(pll->con_reg);
1224 pll_con2 = readl_relaxed(pll->con_reg + 8);
1240 struct samsung_clk_pll *pll = to_clk_pll(hw);
1244 rate = samsung_get_pll_settings(pll, drate);
1246 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1251 pll_con0 = readl_relaxed(pll->con_reg);
1252 pll_con2 = readl_relaxed(pll->con_reg + 8);
1269 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
1271 writel_relaxed(pll_con0, pll->con_reg);
1272 writel_relaxed(pll_con2, pll->con_reg + 8);
1274 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT);
1303 struct samsung_clk_pll *pll = to_clk_pll(hw);
1307 pll_con0 = readl_relaxed(pll->con_reg);
1308 pll_con8 = readl_relaxed(pll->con_reg + 20);
1331 struct samsung_clk_pll *pll;
1335 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1336 if (!pll) {
1337 pr_err("%s: could not allocate pll clk %s\n",
1352 pll->rate_count = len;
1353 pll->rate_table = kmemdup_array(pll_clk->rate_table,
1354 pll->rate_count,
1355 sizeof(*pll->rate_table),
1357 WARN(!pll->rate_table,
1376 pll->enable_offs = PLL35XX_ENABLE_SHIFT;
1377 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
1378 if (!pll->rate_table)
1395 pll->enable_offs = PLL0822X_ENABLE_SHIFT;
1396 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
1397 if (!pll->rate_table)
1407 if (!pll->rate_table)
1415 pll->enable_offs = PLL36XX_ENABLE_SHIFT;
1416 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT;
1417 if (!pll->rate_table)
1423 pll->enable_offs = PLL0831X_ENABLE_SHIFT;
1424 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT;
1425 if (!pll->rate_table)
1441 if (!pll->rate_table)
1450 if (!pll->rate_table)
1456 if (!pll->rate_table)
1462 if (!pll->rate_table)
1472 pr_warn("%s: Unknown pll type for pll clk %s\n",
1476 pll->hw.init = &init;
1477 pll->type = pll_clk->type;
1478 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;
1479 pll->con_reg = ctx->reg_base + pll_clk->con_offset;
1481 ret = clk_hw_register(ctx->dev, &pll->hw);
1483 pr_err("%s: failed to register pll clock %s : %d\n",
1485 kfree(pll->rate_table);
1486 kfree(pll);
1490 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);