Lines Matching +full:0 +full:x10800000
29 /* Register Offset definitions for CMU_TOP (0x11000000) */
30 #define PLL_LOCKTIME_PLL_MMC 0x0004
31 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
32 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
33 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
34 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
35 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
36 #define PLL_LOCKTIME_PLL_SHARED5 0x0018
37 #define PLL_CON0_PLL_MMC 0x0140
38 #define PLL_CON3_PLL_MMC 0x014c
39 #define PLL_CON0_PLL_SHARED0 0x0180
40 #define PLL_CON3_PLL_SHARED0 0x018c
41 #define PLL_CON0_PLL_SHARED1 0x01c0
42 #define PLL_CON3_PLL_SHARED1 0x01cc
43 #define PLL_CON0_PLL_SHARED2 0x0200
44 #define PLL_CON3_PLL_SHARED2 0x020c
45 #define PLL_CON0_PLL_SHARED3 0x0240
46 #define PLL_CON3_PLL_SHARED3 0x024c
47 #define PLL_CON0_PLL_SHARED4 0x0280
48 #define PLL_CON3_PLL_SHARED4 0x028c
49 #define PLL_CON0_PLL_SHARED5 0x02c0
50 #define PLL_CON3_PLL_SHARED5 0x02cc
53 #define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC 0x1000
54 #define CLK_CON_MUX_MUX_CLKCMU_APM_NOC 0x1004
55 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
56 #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x100c
57 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 0x1010
58 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 0x1014
59 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 0x1018
60 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 0x101c
61 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1020
62 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
63 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1028
64 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
65 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
66 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
67 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER 0x1038
68 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x103c
69 #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x1040
70 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
71 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC 0x1048
72 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC 0x104c
73 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x1050
74 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC 0x1054
75 #define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC 0x1058
76 #define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC 0x105c
77 #define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC 0x1060
78 #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x1064
79 #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1068
80 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x106c
81 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x1070
82 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x1074
83 #define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB 0x1078
84 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA 0x107c
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x1080
86 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1084
87 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD 0x1088
88 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET 0x108c
89 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC 0x1090
90 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS 0x1094
91 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x1098
92 #define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC 0x109c
93 #define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG 0x10a0
94 #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x10a4
95 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10a8
96 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x10ac
97 #define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC 0x10b0
98 #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x10b4
99 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10b8
100 #define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC 0x10bc
101 #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x10c0
102 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC 0x10c4
103 #define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC 0x10c8
104 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10cc
105 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x10d0
106 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d4
107 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x10d8
108 #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x10dc
109 #define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC 0x10e0
110 #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x10e4
111 #define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC 0x10e8
112 #define CLK_CON_MUX_MUX_CLK_CMU_NOCP 0x10ec
113 #define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT 0x10f0
114 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
117 #define CLK_CON_DIV_CLKCMU_ACC_NOC 0x1800
118 #define CLK_CON_DIV_CLKCMU_APM_NOC 0x1804
119 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1808
120 #define CLK_CON_DIV_CLKCMU_AUD_NOC 0x180c
121 #define CLK_CON_DIV_CLKCMU_CIS_MCLK0 0x1810
122 #define CLK_CON_DIV_CLKCMU_CIS_MCLK1 0x1814
123 #define CLK_CON_DIV_CLKCMU_CIS_MCLK2 0x1818
124 #define CLK_CON_DIV_CLKCMU_CIS_MCLK3 0x181c
125 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
126 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1824
127 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
128 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
129 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
130 #define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER 0x1834
131 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1838
132 #define CLK_CON_DIV_CLKCMU_DNC_NOC 0x183c
133 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
134 #define CLK_CON_DIV_CLKCMU_DPTX_DPOSC 0x1844
135 #define CLK_CON_DIV_CLKCMU_DPTX_NOC 0x1848
136 #define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x184c
137 #define CLK_CON_DIV_CLKCMU_DPUB_NOC 0x1850
138 #define CLK_CON_DIV_CLKCMU_DPUF0_NOC 0x1854
139 #define CLK_CON_DIV_CLKCMU_DPUF1_NOC 0x1858
140 #define CLK_CON_DIV_CLKCMU_DPUF2_NOC 0x185c
141 #define CLK_CON_DIV_CLKCMU_DSP_NOC 0x1860
142 #define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1864
143 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
144 #define CLK_CON_DIV_CLKCMU_GNPU_NOC 0x186c
145 #define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1870
146 #define CLK_CON_DIV_CLKCMU_ACC_ORB 0x1874
147 #define CLK_CON_DIV_CLKCMU_GNPU_XMAA 0x1878
148 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x187c
149 #define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1880
150 #define CLK_CON_DIV_CLKCMU_HSI1_USBDRD 0x1884
151 #define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET 0x1888
152 #define CLK_CON_DIV_CLKCMU_HSI2_NOC 0x188c
153 #define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS 0x1890
154 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x1894
155 #define CLK_CON_DIV_CLKCMU_ISP_NOC 0x1898
156 #define CLK_CON_DIV_CLKCMU_M2M_JPEG 0x189c
157 #define CLK_CON_DIV_CLKCMU_M2M_NOC 0x18a0
158 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18a4
159 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x18a8
160 #define CLK_CON_DIV_CLKCMU_MFD_NOC 0x18ac
161 #define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x18b0
162 #define CLK_CON_DIV_CLKCMU_MISC_NOC 0x18b4
163 #define CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x18b8
164 #define CLK_CON_DIV_CLKCMU_NOCL1_NOC 0x18bc
165 #define CLK_CON_DIV_CLKCMU_NOCL2_NOC 0x18c0
166 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c4
167 #define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x18c8
168 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18cc
169 #define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x18d0
170 #define CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18d4
171 #define CLK_CON_DIV_CLKCMU_SNW_NOC 0x18d8
172 #define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18dc
173 #define CLK_CON_DIV_CLKCMU_TAA_NOC 0x18e0
174 #define CLK_CON_DIV_CLK_ADD_CH_CLK 0x18e4
175 #define CLK_CON_DIV_CLK_CMU_PLLCLKOUT 0x18e8
176 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18ec
177 #define CLK_CON_DIV_DIV_CLK_CMU_NOCP 0x18f0
564 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
566 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
570 mout_clkcmu_acc_noc_p, CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 0, 3),
572 mout_clkcmu_acc_orb_p, CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 0, 3),
576 mout_clkcmu_apm_noc_p, CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 0, 2),
580 mout_clkcmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
582 mout_clkcmu_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 2),
587 0, 2),
590 0, 3),
593 0, 2),
598 0, 2),
601 0, 3),
606 0, 2),
609 0, 3),
613 mout_clkcmu_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3),
617 mout_clkcmu_dptx_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 0, 2),
619 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
621 mout_clkcmu_dptx_dposc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 0, 1),
625 mout_clkcmu_dpub_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 0, 3),
627 mout_clkcmu_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 1),
631 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 0, 3),
633 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 0, 3),
635 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 0, 3),
639 mout_clkcmu_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3),
643 mout_clkcmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
645 mout_clkcmu_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2),
649 mout_clkcmu_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3),
653 mout_clkcmu_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2),
658 0, 2),
661 0, 2),
664 0, 2),
669 0, 2),
672 0, 2),
675 0, 2),
678 0, 2),
682 mout_clkcmu_isp_noc_p, CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 0, 3),
686 mout_clkcmu_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 2),
688 mout_clkcmu_m2m_jpeg_p, CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 0, 2),
692 mout_clkcmu_mfc_mfc_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
694 mout_clkcmu_mfc_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
698 mout_clkcmu_mfd_noc_p, CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 0, 3),
702 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
704 mout_clkcmu_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2),
708 mout_clkcmu_misc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0, 2),
712 mout_clkcmu_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3),
716 mout_clkcmu_nocl1_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 0, 3),
720 mout_clkcmu_nocl2_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 0, 3),
724 mout_clkcmu_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0, 1),
726 mout_clkcmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
730 mout_clkcmu_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0, 1),
732 mout_clkcmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
736 mout_clkcmu_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3),
740 mout_clkcmu_snw_noc_p, CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 0, 3),
744 mout_clkcmu_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2),
748 mout_clkcmu_taa_noc_p, CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 0, 3),
756 "mout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
760 "mout_clkcmu_acc_noc", CLK_CON_DIV_CLKCMU_ACC_NOC, 0, 4),
762 "mout_clkcmu_acc_orb", CLK_CON_DIV_CLKCMU_ACC_ORB, 0, 4),
766 "mout_clkcmu_apm_noc", CLK_CON_DIV_CLKCMU_APM_NOC, 0, 3),
770 "mout_clkcmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
772 "mout_clkcmu_aud_noc", CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4),
777 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
780 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 0, 3),
783 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
788 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
791 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 0, 3),
796 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
799 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 0, 3),
803 "mout_clkcmu_dnc_noc", CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4),
807 "mout_clkcmu_dptx_noc", CLK_CON_DIV_CLKCMU_DPTX_NOC, 0, 4),
809 "mout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
811 "mout_clkcmu_dptx_dposc", CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 0, 5),
815 "mout_clkcmu_dpub_noc", CLK_CON_DIV_CLKCMU_DPUB_NOC, 0, 4),
817 "mout_clkcmu_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4),
821 "mout_clkcmu_dpuf0_noc", CLK_CON_DIV_CLKCMU_DPUF0_NOC, 0, 4),
823 "mout_clkcmu_dpuf1_noc", CLK_CON_DIV_CLKCMU_DPUF1_NOC, 0, 4),
825 "mout_clkcmu_dpuf2_noc", CLK_CON_DIV_CLKCMU_DPUF2_NOC, 0, 4),
829 "mout_clkcmu_dsp_noc", CLK_CON_DIV_CLKCMU_DSP_NOC, 0, 4),
833 "mout_clkcmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
835 "mout_clkcmu_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3),
839 "mout_clkcmu_gnpu_noc", CLK_CON_DIV_CLKCMU_GNPU_NOC, 0, 4),
843 "mout_clkcmu_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4),
847 "mout_clkcmu_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4),
849 "mout_clkcmu_hsi1_usbdrd", CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 0, 4),
851 "mout_clkcmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9),
855 "mout_clkcmu_hsi2_noc", CLK_CON_DIV_CLKCMU_HSI2_NOC, 0, 4),
857 "mout_clkcmu_hsi2_noc_ufs", CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 0, 4),
859 "mout_clkcmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 3),
861 "mout_clkcmu_hsi2_ethernet", CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 0, 3),
865 "mout_clkcmu_isp_noc", CLK_CON_DIV_CLKCMU_ISP_NOC, 0, 4),
869 "mout_clkcmu_m2m_noc", CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4),
871 "mout_clkcmu_m2m_jpeg", CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4),
875 "mout_clkcmu_mfc_mfc", CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
877 "mout_clkcmu_mfc_wfd", CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
881 "mout_clkcmu_mfd_noc", CLK_CON_DIV_CLKCMU_MFD_NOC, 0, 4),
885 "mout_clkcmu_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4),
889 "mout_clkcmu_misc_noc", CLK_CON_DIV_CLKCMU_MISC_NOC, 0, 4),
893 "mout_clkcmu_nocl0_noc", CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4),
897 "mout_clkcmu_nocl1_noc", CLK_CON_DIV_CLKCMU_NOCL1_NOC, 0, 4),
901 "mout_clkcmu_nocl2_noc", CLK_CON_DIV_CLKCMU_NOCL2_NOC, 0, 4),
905 "mout_clkcmu_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4),
907 "mout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
911 "mout_clkcmu_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4),
913 "mout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
917 "mout_clkcmu_sdma_noc", CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4),
921 "mout_clkcmu_snw_noc", CLK_CON_DIV_CLKCMU_SNW_NOC, 0, 4),
925 "mout_clkcmu_ssp_noc", CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4),
929 "mout_clkcmu_taa_noc", CLK_CON_DIV_CLKCMU_TAA_NOC, 0, 4),
934 "mout_shared0_pll", 1, 1, 0),
936 "mout_shared0_pll", 1, 2, 0),
938 "mout_shared0_pll", 1, 3, 0),
940 "mout_shared0_pll", 1, 4, 0),
942 "mout_shared1_pll", 1, 1, 0),
944 "mout_shared1_pll", 1, 2, 0),
946 "mout_shared1_pll", 1, 3, 0),
948 "mout_shared1_pll", 1, 4, 0),
950 "mout_shared2_pll", 1, 1, 0),
952 "mout_shared2_pll", 1, 2, 0),
954 "mout_shared2_pll", 1, 3, 0),
956 "mout_shared2_pll", 1, 4, 0),
958 "mout_shared3_pll", 1, 1, 0),
960 "mout_shared3_pll", 1, 2, 0),
962 "mout_shared3_pll", 1, 3, 0),
964 "mout_shared3_pll", 1, 4, 0),
966 "mout_shared4_pll", 1, 1, 0),
968 "mout_shared4_pll", 1, 2, 0),
970 "mout_shared4_pll", 1, 3, 0),
972 "mout_shared4_pll", 1, 4, 0),
974 "mout_shared5_pll", 1, 1, 0),
976 "mout_shared5_pll", 1, 2, 0),
978 "mout_shared5_pll", 1, 3, 0),
980 "mout_shared5_pll", 1, 4, 0),
982 "oscclk", 1, 2, 0),
1010 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
1011 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0600
1012 #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x0610
1013 #define CLK_CON_MUX_MUX_CLK_PERIC0_I3C 0x1000
1014 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1004
1015 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1008
1016 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x100c
1017 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x1010
1018 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1014
1019 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1018
1020 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI 0x101c
1021 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI 0x1020
1022 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI 0x1024
1023 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1028
1024 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
1025 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804
1026 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808
1027 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c
1028 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810
1029 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814
1030 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818
1031 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI 0x181c
1032 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI 0x1820
1033 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI 0x1824
1034 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828
1075 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1077 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1079 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1081 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1083 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1085 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1087 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 0, 1),
1089 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 0, 1),
1091 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 0, 1),
1094 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1097 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 0, 1),
1104 0, 4),
1107 0, 4),
1110 0, 4),
1113 0, 4),
1116 0, 4),
1119 0, 4),
1122 0, 4),
1125 0, 4),
1128 0, 4),
1131 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1134 "mout_peric0_i3c", CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
1150 /* Register Offset definitions for CMU_PERIC1 (0x10C00000) */
1151 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600
1152 #define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610
1153 #define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000
1154 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004
1155 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008
1156 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c
1157 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010
1158 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014
1159 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018
1160 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c
1161 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020
1162 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024
1163 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028
1164 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
1165 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804
1166 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
1167 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
1168 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
1169 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
1170 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818
1171 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c
1172 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
1173 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
1174 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828
1215 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1217 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1219 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1221 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),
1223 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),
1225 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),
1227 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),
1229 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),
1231 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),
1234 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1237 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),
1244 0, 4),
1247 0, 4),
1250 0, 4),
1253 0, 4),
1256 0, 4),
1259 0, 4),
1262 0, 4),
1265 0, 4),
1268 0, 4),
1271 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1274 "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
1290 /* Register Offset definitions for CMU_MISC (0x10020000) */
1291 #define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600
1292 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
1293 #define CLK_CON_DIV_CLKCMU_OTP 0x1800
1294 #define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804
1295 #define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808
1313 mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),
1319 0, 3),
1324 "oscclk", 1, 10, 0),
1326 "oscclk", 1, 2, 0),
1344 /* Register Offset definitions for CMU_HSI0 (0x16000000) */
1345 #define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600
1346 #define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800
1364 0, 4),
1380 /* Register Offset definitions for CMU_HSI1 (0x16400000) */
1381 #define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600
1382 #define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610
1383 #define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620
1384 #define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000
1427 return 0; in exynosautov920_cmu_probe()