Lines Matching +full:0 +full:x10800000
29 /* Register Offset definitions for CMU_TOP (0x15a80000) */
30 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
31 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
32 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
33 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
34 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
35 #define PLL_CON0_MUX_CP2AP_MIF_CLK_USER 0x0100
36 #define PLL_CON2_MUX_CP2AP_MIF_CLK_USER 0x0108
37 #define PLL_CON0_PLL_SHARED0 0x0120
38 #define PLL_CON0_PLL_SHARED1 0x0140
39 #define PLL_CON0_PLL_SHARED2 0x0160
40 #define PLL_CON0_PLL_SHARED3 0x0180
41 #define PLL_CON0_PLL_SHARED4 0x01a0
42 #define CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX 0x1000
43 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
44 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
45 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x100c
46 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C 0x1010
47 #define CLK_CON_MUX_MUX_CLKCMU_CAM_BUS 0x1014
48 #define CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0 0x1018
49 #define CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1 0x101c
50 #define CLK_CON_MUX_MUX_CLKCMU_CAM_VRA 0x1020
51 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1024
52 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1028
53 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x102c
54 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x1030
55 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1034
56 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1038
57 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x103c
58 #define CLK_CON_MUX_MUX_CLKCMU_DBG_BUS 0x1040
59 #define CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS 0x1044
60 #define CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD 0x1048
61 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x104c
62 #define CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR 0x1050
63 #define CLK_CON_MUX_MUX_CLKCMU_DSP_BUS 0x1054
64 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1058
65 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC 0x105c
66 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD 0x1060
67 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD 0x1064
68 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30 0x1068
69 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x106c
70 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1070
71 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE 0x1074
72 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD 0x1078
73 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x107c
74 #define CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG 0x1080
75 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
76 #define CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS 0x1088
77 #define CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS 0x108c
78 #define CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS 0x1090
79 #define CLK_CON_MUX_MUX_CLKCMU_IVA_BUS 0x1094
80 #define CLK_CON_MUX_MUX_CLKCMU_MFC_BUS 0x1098
81 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
82 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a0
83 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG 0x10a4
84 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00 0x10a8
85 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01 0x10ac
86 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02 0x10b0
87 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03 0x10b4
88 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10b8
89 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2 0x10bc
90 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0 0x10c0
91 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1 0x10c4
92 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT 0x10c8
93 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04 0x10cc
94 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05 0x10d0
95 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06 0x10d4
96 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07 0x10d8
97 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08 0x10dc
98 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09 0x10e0
99 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10 0x10e4
100 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11 0x10e8
101 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12 0x10ec
102 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13 0x10f0
103 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10f4
104 #define CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS 0x10f8
105 #define CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD 0x10fc
106 #define CLK_CON_MUX_MUX_CLKCMU_VPU_BUS 0x1100
107 #define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x1104
108 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
109 #define CLK_CON_DIV_CLKCMU_ABOX_CPUABOX 0x1800
110 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
111 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
112 #define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x180c
113 #define CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C 0x1810
114 #define CLK_CON_DIV_CLKCMU_CAM_BUS 0x1814
115 #define CLK_CON_DIV_CLKCMU_CAM_TPU0 0x1818
116 #define CLK_CON_DIV_CLKCMU_CAM_TPU1 0x181c
117 #define CLK_CON_DIV_CLKCMU_CAM_VRA 0x1820
118 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1824
119 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1828
120 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x182c
121 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x1830
122 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1834
123 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
124 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
125 #define CLK_CON_DIV_CLKCMU_DBG_BUS 0x1840
126 #define CLK_CON_DIV_CLKCMU_DCAM_BUS 0x1844
127 #define CLK_CON_DIV_CLKCMU_DCAM_IMGD 0x1848
128 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x184c
129 #define CLK_CON_DIV_CLKCMU_DSP_BUS 0x1850
130 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1854
131 #define CLK_CON_DIV_CLKCMU_FSYS0_DPGTC 0x1858
132 #define CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD 0x185c
133 #define CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD 0x1860
134 #define CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30 0x1864
135 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1868
136 #define CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD 0x186c
137 #define CLK_CON_DIV_CLKCMU_FSYS1_PCIE 0x1870
138 #define CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD 0x1874
139 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1878
140 #define CLK_CON_DIV_CLKCMU_G2D_JPEG 0x187c
141 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1880
142 #define CLK_CON_DIV_CLKCMU_HPM 0x1884
143 #define CLK_CON_DIV_CLKCMU_IMEM_BUS 0x1888
144 #define CLK_CON_DIV_CLKCMU_ISPHQ_BUS 0x188c
145 #define CLK_CON_DIV_CLKCMU_ISPLP_BUS 0x1890
146 #define CLK_CON_DIV_CLKCMU_IVA_BUS 0x1894
147 #define CLK_CON_DIV_CLKCMU_MFC_BUS 0x1898
148 #define CLK_CON_DIV_CLKCMU_MODEM_SHARED0 0x189c
149 #define CLK_CON_DIV_CLKCMU_MODEM_SHARED1 0x18a0
150 #define CLK_CON_DIV_CLKCMU_OTP 0x18a4
151 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18a8
152 #define CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG 0x18ac
153 #define CLK_CON_DIV_CLKCMU_PERIC0_USI00 0x18b0
154 #define CLK_CON_DIV_CLKCMU_PERIC0_USI01 0x18b4
155 #define CLK_CON_DIV_CLKCMU_PERIC0_USI02 0x18b8
156 #define CLK_CON_DIV_CLKCMU_PERIC0_USI03 0x18bc
157 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18c0
158 #define CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2 0x18c4
159 #define CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0 0x18c8
160 #define CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1 0x18cc
161 #define CLK_CON_DIV_CLKCMU_PERIC1_UART_BT 0x18d0
162 #define CLK_CON_DIV_CLKCMU_PERIC1_USI04 0x18d4
163 #define CLK_CON_DIV_CLKCMU_PERIC1_USI05 0x18d8
164 #define CLK_CON_DIV_CLKCMU_PERIC1_USI06 0x18dc
165 #define CLK_CON_DIV_CLKCMU_PERIC1_USI07 0x18e0
166 #define CLK_CON_DIV_CLKCMU_PERIC1_USI08 0x18e4
167 #define CLK_CON_DIV_CLKCMU_PERIC1_USI09 0x18e8
168 #define CLK_CON_DIV_CLKCMU_PERIC1_USI10 0x18ec
169 #define CLK_CON_DIV_CLKCMU_PERIC1_USI11 0x18f0
170 #define CLK_CON_DIV_CLKCMU_PERIC1_USI12 0x18f4
171 #define CLK_CON_DIV_CLKCMU_PERIC1_USI13 0x18f8
172 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18fc
173 #define CLK_CON_DIV_CLKCMU_SRDZ_BUS 0x1900
174 #define CLK_CON_DIV_CLKCMU_SRDZ_IMGD 0x1904
175 #define CLK_CON_DIV_CLKCMU_VPU_BUS 0x1908
176 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x190c
177 #define CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2 0x1910
178 #define CLK_CON_DIV_DIV_PLL_SHARED0_DIV2 0x1914
179 #define CLK_CON_DIV_DIV_PLL_SHARED0_DIV4 0x1918
180 #define CLK_CON_DIV_DIV_PLL_SHARED1_DIV2 0x191c
181 #define CLK_CON_DIV_DIV_PLL_SHARED1_DIV4 0x1920
182 #define CLK_CON_DIV_DIV_PLL_SHARED2_DIV2 0x1924
183 #define CLK_CON_DIV_DIV_PLL_SHARED3_DIV2 0x1928
184 #define CLK_CON_DIV_DIV_PLL_SHARED4_DIV2 0x192c
185 #define CLK_CON_GAT_CLKCMU_DROOPDETECTOR 0x2000
186 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2004
187 #define CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX 0x2008
188 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x200c
189 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x2010
190 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x2014
191 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C 0x2018
192 #define CLK_CON_GAT_GATE_CLKCMU_CAM_BUS 0x201c
193 #define CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0 0x2020
194 #define CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1 0x2024
195 #define CLK_CON_GAT_GATE_CLKCMU_CAM_VRA 0x2028
196 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x202c
197 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2030
198 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2034
199 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2038
200 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x203c
201 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2040
202 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2044
203 #define CLK_CON_GAT_GATE_CLKCMU_DBG_BUS 0x2048
204 #define CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS 0x204c
205 #define CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD 0x2050
206 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2054
207 #define CLK_CON_GAT_GATE_CLKCMU_DSP_BUS 0x2058
208 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x205c
209 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC 0x2060
210 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD 0x2064
211 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD 0x2068
212 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30 0x206c
213 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2070
214 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2074
215 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE 0x2078
216 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD 0x207c
217 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
218 #define CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG 0x2084
219 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2088
220 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x208c
221 #define CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS 0x2090
222 #define CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS 0x2094
223 #define CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS 0x2098
224 #define CLK_CON_GAT_GATE_CLKCMU_IVA_BUS 0x209c
225 #define CLK_CON_GAT_GATE_CLKCMU_MFC_BUS 0x20a0
226 #define CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0 0x20a4
227 #define CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1 0x20a8
228 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20ac
229 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG 0x20b0
230 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00 0x20b4
231 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01 0x20b8
232 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02 0x20bc
233 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03 0x20c0
234 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20c4
235 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2 0x20c8
236 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0 0x20cc
237 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1 0x20d0
238 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT 0x20d4
239 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04 0x20d8
240 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05 0x20dc
241 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06 0x20e0
242 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07 0x20e4
243 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08 0x20e8
244 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09 0x20ec
245 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10 0x20f0
246 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11 0x20f4
247 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12 0x20f8
248 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13 0x20fc
249 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x2100
250 #define CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS 0x2104
251 #define CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD 0x2108
252 #define CLK_CON_GAT_GATE_CLKCMU_VPU_BUS 0x210c
481 PLL_35XX_RATE(26 * MHZ, 2132000000U, 328, 4, 0),
485 PLL_35XX_RATE(26 * MHZ, 1865500000U, 287, 4, 0),
489 PLL_35XX_RATE(26 * MHZ, 800000000U, 400, 13, 0),
493 PLL_35XX_RATE(26 * MHZ, 630000000U, 315, 13, 0),
497 PLL_35XX_RATE(26 * MHZ, 667333333U, 154, 6, 0),
783 0, 2),
785 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
787 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
789 CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 3),
792 0, 2),
794 CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, 0, 2),
796 CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0, 0, 2),
798 CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1, 0, 2),
800 CLK_CON_MUX_MUX_CLKCMU_CAM_VRA, 0, 2),
802 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
804 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
806 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
808 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
810 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
813 0, 2),
816 0, 2),
818 CLK_CON_MUX_MUX_CLKCMU_DBG_BUS, 0, 2),
820 CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS, 0, 2),
822 CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD, 0, 2),
824 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3),
827 0, 2),
829 CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2),
831 CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
833 CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC, 0, 2),
836 0, 3),
839 0, 2),
842 0, 2),
844 CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 1),
847 0, 3),
849 mout_cmu_fsys1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE, 0, 1),
852 0, 2),
854 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
856 CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG, 0, 2),
858 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
860 CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS, 0, 2),
862 CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS, 0, 2),
864 CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS, 0, 2),
866 CLK_CON_MUX_MUX_CLKCMU_IVA_BUS, 0, 2),
868 CLK_CON_MUX_MUX_CLKCMU_MFC_BUS, 0, 2),
870 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
872 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
875 0, 2),
878 0, 2),
881 0, 2),
884 0, 2),
887 0, 2),
889 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
892 0, 2),
895 0, 2),
898 0, 2),
901 0, 2),
904 0, 2),
907 0, 2),
910 0, 2),
913 0, 2),
916 0, 2),
919 0, 2),
922 0, 2),
925 0, 2),
928 0, 2),
931 0, 2),
933 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
935 CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS, 0, 2),
937 CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD, 0, 2),
939 CLK_CON_MUX_MUX_CLKCMU_VPU_BUS, 0, 2),
944 "gout_cmu_abox_cpuabox", CLK_CON_DIV_CLKCMU_ABOX_CPUABOX, 0, 3),
946 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
948 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
950 "gout_cmu_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
953 0, 4),
955 CLK_CON_DIV_CLKCMU_CAM_BUS, 0, 4),
957 CLK_CON_DIV_CLKCMU_CAM_TPU0, 0, 4),
959 CLK_CON_DIV_CLKCMU_CAM_TPU1, 0, 4),
961 CLK_CON_DIV_CLKCMU_CAM_VRA, 0, 4),
963 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
965 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
967 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
969 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
971 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
973 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
975 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
977 CLK_CON_DIV_CLKCMU_DBG_BUS, 0, 4),
979 CLK_CON_DIV_CLKCMU_DCAM_BUS, 0, 4),
981 CLK_CON_DIV_CLKCMU_DCAM_IMGD, 0, 4),
983 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
985 CLK_CON_DIV_CLKCMU_DSP_BUS, 0, 4),
987 CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
989 "gout_cmu_fsys0_dpgtc", CLK_CON_DIV_CLKCMU_FSYS0_DPGTC, 0, 3),
992 0, 9),
995 0, 3),
998 0, 4),
1000 CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
1003 0, 9),
1006 0, 4),
1008 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
1010 CLK_CON_DIV_CLKCMU_G2D_JPEG, 0, 4),
1012 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
1014 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
1016 CLK_CON_DIV_CLKCMU_IMEM_BUS, 0, 4),
1018 CLK_CON_DIV_CLKCMU_ISPHQ_BUS, 0, 4),
1020 CLK_CON_DIV_CLKCMU_ISPLP_BUS, 0, 4),
1022 CLK_CON_DIV_CLKCMU_IVA_BUS, 0, 4),
1024 CLK_CON_DIV_CLKCMU_MFC_BUS, 0, 4),
1026 "gout_cmu_modem_shared0", CLK_CON_DIV_CLKCMU_MODEM_SHARED0, 0, 3),
1028 "gout_cmu_modem_shared1", CLK_CON_DIV_CLKCMU_MODEM_SHARED1, 0, 3),
1030 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
1033 0, 4),
1035 "gout_cmu_peric0_usi00", CLK_CON_DIV_CLKCMU_PERIC0_USI00, 0, 4),
1037 "gout_cmu_peric0_usi01", CLK_CON_DIV_CLKCMU_PERIC0_USI01, 0, 4),
1039 "gout_cmu_peric0_usi02", CLK_CON_DIV_CLKCMU_PERIC0_USI02, 0, 4),
1041 "gout_cmu_peric0_usi03", CLK_CON_DIV_CLKCMU_PERIC0_USI03, 0, 4),
1043 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
1046 0, 4),
1049 0, 4),
1052 0, 4),
1055 0, 4),
1057 "gout_cmu_peric1_usi04", CLK_CON_DIV_CLKCMU_PERIC1_USI04, 0, 4),
1059 "gout_cmu_peric1_usi05", CLK_CON_DIV_CLKCMU_PERIC1_USI05, 0, 4),
1061 "gout_cmu_peric1_usi06", CLK_CON_DIV_CLKCMU_PERIC1_USI06, 0, 4),
1063 "gout_cmu_peric1_usi07", CLK_CON_DIV_CLKCMU_PERIC1_USI07, 0, 4),
1065 "gout_cmu_peric1_usi08", CLK_CON_DIV_CLKCMU_PERIC1_USI08, 0, 4),
1067 "gout_cmu_peric1_usi09", CLK_CON_DIV_CLKCMU_PERIC1_USI09, 0, 4),
1069 "gout_cmu_peric1_usi10", CLK_CON_DIV_CLKCMU_PERIC1_USI10, 0, 4),
1071 "gout_cmu_peric1_usi11", CLK_CON_DIV_CLKCMU_PERIC1_USI11, 0, 4),
1073 "gout_cmu_peric1_usi12", CLK_CON_DIV_CLKCMU_PERIC1_USI12, 0, 4),
1075 "gout_cmu_peric1_usi13", CLK_CON_DIV_CLKCMU_PERIC1_USI13, 0, 4),
1077 CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
1079 CLK_CON_DIV_CLKCMU_SRDZ_BUS, 0, 4),
1081 CLK_CON_DIV_CLKCMU_SRDZ_IMGD, 0, 4),
1083 CLK_CON_DIV_CLKCMU_VPU_BUS, 0, 4),
1088 "mout_pll_shared0", 1, 2, 0),
1090 "mout_pll_shared0", 1, 4, 0),
1092 "mout_pll_shared1", 1, 2, 0),
1094 "mout_pll_shared1", 1, 4, 0),
1096 "mout_pll_shared2", 1, 2, 0),
1098 "mout_pll_shared3", 1, 2, 0),
1100 "mout_pll_shared4", 1, 2, 0),
1102 "gout_cmu_fsys1_pcie", 1, 8, 0),
1104 "mout_cp2ap_mif_clk_user", 1, 2, 0),
1105 FFACTOR(CLK_DOUT_CMU_CMU_OTP, "dout_cmu_cmu_otp", "oscclk", 1, 8, 0),
1111 21, 0, 0),
1113 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1116 21, 0, 0),
1118 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
1120 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, CLK_IGNORE_UNUSED, 0),
1122 CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21, CLK_IGNORE_UNUSED, 0),
1125 21, CLK_IGNORE_UNUSED, 0),
1127 CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, 21, 0, 0),
1129 CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0, 21, 0, 0),
1131 CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1, 21, 0, 0),
1133 CLK_CON_GAT_GATE_CLKCMU_CAM_VRA, 21, 0, 0),
1135 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1137 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1139 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1141 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1143 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, CLK_IGNORE_UNUSED, 0),
1146 21, CLK_IGNORE_UNUSED, 0),
1149 21, CLK_IGNORE_UNUSED, 0),
1151 CLK_CON_GAT_GATE_CLKCMU_DBG_BUS, 21, 0, 0),
1153 CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS, 21, 0, 0),
1156 21, 0, 0),
1158 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, CLK_IGNORE_UNUSED, 0),
1160 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS, 21, CLK_IGNORE_UNUSED, 0),
1162 CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS, 21, 0, 0),
1165 21, 0, 0),
1168 21, 0, 0),
1171 21, 0, 0),
1174 21, 0, 0),
1177 21, 0, 0),
1180 21, 0, 0),
1183 21, 0, 0),
1186 21, 0, 0),
1188 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1190 CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG, 21, 0, 0),
1192 "fout_shared2_pll", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
1194 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1196 CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS, 21, 0, 0),
1199 21, 0, 0),
1202 21, 0, 0),
1204 CLK_CON_GAT_GATE_CLKCMU_IVA_BUS, 21, 0, 0),
1206 CLK_CON_GAT_GATE_CLKCMU_MFC_BUS, 21, 0, 0),
1209 21, 0, 0),
1212 21, 0, 0),
1215 21, 0, 0),
1218 CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG, 21, 0, 0),
1221 21, 0, 0),
1224 21, 0, 0),
1227 21, 0, 0),
1230 21, 0, 0),
1233 21, 0, 0),
1236 21, 0, 0),
1239 CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0, 21, 0, 0),
1242 CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1, 21, 0, 0),
1245 21, 0, 0),
1248 21, 0, 0),
1251 21, 0, 0),
1254 21, 0, 0),
1257 21, 0, 0),
1260 21, 0, 0),
1263 21, 0, 0),
1266 21, 0, 0),
1269 21, 0, 0),
1272 21, 0, 0),
1275 21, 0, 0),
1278 21, 0, 0),
1280 CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS, 21, 0, 0),
1283 21, 0, 0),
1285 CLK_CON_GAT_GATE_CLKCMU_VPU_BUS, 21, 0, 0),
1315 /* Register Offset definitions for CMU_PERIS (0x10010000) */
1316 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0100
1317 #define PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER 0x0108
1318 #define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000
1319 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x2000
1320 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM 0x2010
1321 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS 0x2014
1322 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK 0x2018
1323 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK 0x201c
1324 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK 0x2020
1325 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK 0x2024
1326 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK 0x2028
1327 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x202c
1328 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2030
1329 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2034
1330 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK 0x2038
1331 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK 0x203c
1332 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2040
1333 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2044
1334 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK 0x2048
1335 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK 0x204c
1336 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK 0x2050
1337 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK 0x2054
1338 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK 0x2058
1339 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK 0x205c
1340 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK 0x2060
1341 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK 0x2064
1342 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK 0x2068
1343 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK 0x206c
1344 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK 0x2070
1345 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK 0x2074
1346 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK 0x2078
1347 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK 0x207c
1348 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK 0x2080
1349 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK 0x2084
1350 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2088
1351 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x208c
1352 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK 0x2090
1402 mout_peris_gic_p, CLK_CON_MUX_MUX_CLK_PERIS_GIC, 0, 5),
1409 21, CLK_IS_CRITICAL, 0),
1413 21, CLK_IS_CRITICAL, 0),
1417 21, CLK_IS_CRITICAL, 0),
1421 21, CLK_IS_CRITICAL, 0),
1425 21, CLK_IS_CRITICAL, 0),
1429 21, 0, 0),
1434 21, CLK_IS_CRITICAL, 0),
1438 21, CLK_IS_CRITICAL, 0),
1441 CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, 21, 0, 0),
1445 21, 0, 0),
1449 21, 0, 0),
1453 21, 0, 0),
1457 21, 0, 0),
1461 21, 0, 0),
1465 21, 0, 0),
1468 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK, 21, 0, 0),
1471 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK, 21, 0, 0),
1474 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK, 21, 0, 0),
1477 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK, 21, 0, 0),
1480 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK, 21, 0, 0),
1483 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK, 21, 0, 0),
1486 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK, 21, 0, 0),
1489 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK, 21, 0, 0),
1492 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK, 21, 0, 0),
1495 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK, 21, 0, 0),
1498 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK, 21, 0, 0),
1501 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK, 21, 0, 0),
1504 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK, 21, 0, 0),
1507 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK, 21, 0, 0),
1510 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK, 21, 0, 0),
1513 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK, 21, 0, 0),
1517 21, 0, 0),
1521 21, 0, 0),
1525 21, CLK_IGNORE_UNUSED, 0),
1550 /* Register Offset definitions for CMU_FSYS0 (0x11000000) */
1551 #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0100
1552 #define PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER 0x0108
1553 #define PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER 0x0120
1554 #define PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER 0x0128
1555 #define PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER 0x0140
1556 #define PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER 0x0148
1557 #define PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER 0x0160
1558 #define PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER 0x0168
1559 #define PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER 0x0180
1560 #define PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER 0x0188
1561 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
1562 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2010
1563 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK 0x2014
1564 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK 0x2018
1565 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x201c
1566 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK 0x2020
1567 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK 0x2024
1568 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK 0x202c
1569 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2030
1570 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2034
1571 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x2038
1572 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK 0x203c
1573 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK 0x2040
1574 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK 0x2044
1575 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK 0x2048
1576 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK 0x204c
1577 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK 0x2050
1578 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN 0x2054
1579 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK 0x2058
1580 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK 0x205c
1581 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK 0x2060
1582 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK 0x2064
1583 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK 0x2068
1584 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x206c
1585 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x2070
1586 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x2074
1587 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK 0x2078
1588 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK 0x207c
1589 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK 0x2080
1590 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK 0x2084
1591 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK 0x2088
1592 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK 0x208c
1593 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK 0x2090
1594 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK 0x2094
1595 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK 0x2098
1596 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK 0x209c
1665 4, 1, CLK_SET_RATE_PARENT, 0),
1679 21, CLK_IS_CRITICAL, 0),
1683 21, 0, 0),
1687 21, CLK_IS_CRITICAL, 0),
1691 21, CLK_IS_CRITICAL, 0),
1695 21, CLK_IS_CRITICAL, 0),
1699 21, 0, 0),
1703 21, 0, 0),
1707 21, 0, 0),
1711 21, 0, 0),
1714 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0),
1717 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0),
1721 21, CLK_IGNORE_UNUSED, 0),
1725 21, 0, 0),
1729 21, 0, 0),
1733 21, CLK_IS_CRITICAL, 0),
1737 21, CLK_IS_CRITICAL, 0),
1741 21, 0, 0),
1745 21, CLK_SET_RATE_PARENT, 0),
1748 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK, 21, 0, 0),
1751 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK, 21, 0, 0),
1754 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK, 21, 0, 0),
1758 21, 0, 0),
1762 21, 0, 0),
1766 21, 0, 0),
1770 21, CLK_IS_CRITICAL, 0),
1774 21, 0, 0),
1778 21, 0, 0),
1782 21, 0, 0),
1787 21, 0, 0),
1791 21, 0, 0),
1795 21, 0, 0),
1799 21, 0, 0),
1803 21, 0, 0),
1807 21, CLK_IGNORE_UNUSED, 0),
1811 21, CLK_IGNORE_UNUSED, 0),
1815 21, CLK_IGNORE_UNUSED, 0),
1831 /* Register Offset definitions for CMU_FSYS1 (0x11400000) */
1832 #define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0100
1833 #define PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER 0x0108
1834 #define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0120
1835 #define PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0128
1836 #define PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER 0x0140
1837 #define PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER 0x0148
1838 #define PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER 0x0160
1839 #define PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER 0x0168
1840 #define CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN 0x2000
1841 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2004
1842 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK 0x2008
1843 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK 0x200c
1844 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK 0x2010
1845 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK 0x2014
1846 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK 0x2018
1847 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK 0x201c
1848 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2024
1849 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK 0x2028
1850 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK 0x202c
1851 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK 0x2030
1852 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
1853 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
1854 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0 0x203c
1855 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1 0x2040
1856 …_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK 0x2044
1857 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0 0x2048
1858 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1 0x204c
1859 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2050
1860 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK 0x2054
1861 …e CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL 0x2058
1862 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0 0x205c
1863 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1 0x2060
1864 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK 0x2068
1865 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK 0x206c
1866 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK 0x2070
1867 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK 0x2074
1868 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK 0x207c
1869 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK 0x2080
1870 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK 0x2084
1871 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK 0x2088
1872 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK 0x2090
1873 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK 0x2094
1874 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK 0x2098
1875 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK 0x209c
1876 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO 0x20a0
1877 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK 0x20a4
1878 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK 0x20a8
1879 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK 0x20ac
1946 4, 1, CLK_SET_RATE_PARENT, 0),
1958 21, 0, 0),
1962 21, 0, 0),
1966 21, CLK_IS_CRITICAL, 0),
1970 21, CLK_IS_CRITICAL, 0),
1974 21, CLK_IS_CRITICAL, 0),
1978 21, CLK_IS_CRITICAL, 0),
1982 21, 0, 0),
1986 21, 0, 0),
1990 21, CLK_IS_CRITICAL, 0),
1994 21, CLK_IGNORE_UNUSED, 0),
1998 21, CLK_IS_CRITICAL, 0),
2002 21, CLK_IS_CRITICAL, 0),
2006 21, 0, 0),
2010 21, CLK_SET_RATE_PARENT, 0),
2014 21, 0, 0),
2018 21, 0, 0),
2023 21, 0, 0),
2027 21, 0, 0),
2031 21, 0, 0),
2036 21, 0, 0),
2041 21, 0, 0),
2046 21, 0, 0),
2050 21, 0, 0),
2054 21, 0, 0),
2058 21, 0, 0),
2062 21, 0, 0),
2066 21, 0, 0),
2070 21, 0, 0),
2073 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK, 21, 0, 0),
2076 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK, 21, 0, 0),
2079 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK, 21, 0, 0),
2082 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK, 21, 0, 0),
2086 21, 0, 0),
2090 21, 0, 0),
2094 21, 0, 0),
2098 21, 0, 0),
2102 21, CLK_IGNORE_UNUSED, 0),
2106 21, 0, 0),
2110 21, CLK_IGNORE_UNUSED, 0),
2114 21, CLK_IGNORE_UNUSED, 0),
2130 /* Register Offset definitions for CMU_PERIC0 (0x10400000) */
2131 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0100
2132 #define PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER 0x0108
2133 #define PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER 0x0120
2134 #define PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER 0x0128
2135 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER 0x0140
2136 #define PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER 0x0148
2137 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER 0x0160
2138 #define PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER 0x0168
2139 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER 0x0180
2140 #define PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER 0x0188
2141 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER 0x01a0
2142 #define PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER 0x01a8
2143 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2000
2144 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2014
2145 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2018
2146 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x201c
2147 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK 0x2020
2148 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0 0x2028
2149 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x202c
2150 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK 0x2030
2151 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x2034
2152 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK 0x2038
2153 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK 0x203c
2154 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK 0x2040
2155 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI 0x2044
2156 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK 0x2048
2157 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI 0x204c
2158 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK 0x2050
2159 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI 0x2054
2160 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK 0x2058
2161 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI 0x205c
2234 21, CLK_IS_CRITICAL, 0),
2238 21, CLK_IS_CRITICAL, 0),
2242 21, CLK_IGNORE_UNUSED, 0),
2246 21, CLK_IS_CRITICAL, 0),
2250 21, 0, 0),
2254 21, 0, 0),
2259 21, 0, 0),
2263 21, 0, 0),
2267 21, 0, 0),
2271 21, 0, 0),
2275 21, 0, 0),
2278 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK, 21, 0, 0),
2282 21, 0, 0),
2285 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK, 21, 0, 0),
2289 21, 0, 0),
2292 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK, 21, 0, 0),
2296 21, 0, 0),
2299 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK, 21, 0, 0),
2303 21, 0, 0),
2319 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
2320 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0100
2321 #define PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER 0x0108
2322 #define PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER 0x0120
2323 #define PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER 0x0128
2324 #define PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER 0x0140
2325 #define PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER 0x0148
2326 #define PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER 0x0160
2327 #define PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER 0x0168
2328 #define PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0180
2329 #define PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0188
2330 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER 0x01a0
2331 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER 0x01a8
2332 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER 0x01c0
2333 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER 0x01c8
2334 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER 0x01e0
2335 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER 0x01e8
2336 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER 0x0200
2337 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER 0x0208
2338 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER 0x0220
2339 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER 0x0228
2340 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER 0x0240
2341 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER 0x0248
2342 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER 0x0260
2343 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER 0x0268
2344 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER 0x0280
2345 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER 0x0288
2346 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER 0x02a0
2347 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER 0x02a8
2348 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER 0x02c0
2349 #define PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER 0x02c8
2350 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2000
2351 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK 0x200c
2352 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK 0x201c
2353 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK 0x2020
2354 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK 0x2024
2355 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2028
2356 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK 0x202c
2357 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK 0x2030
2358 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK 0x2034
2359 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK 0x2038
2360 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x203c
2361 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK 0x2040
2362 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x2044
2363 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK 0x2048
2364 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK 0x204c
2365 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK 0x2050
2366 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK 0x2054
2367 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK 0x2058
2368 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK 0x205c
2369 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK 0x2060
2370 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK 0x2064
2371 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK 0x2068
2372 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK 0x206c
2373 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK 0x2070
2374 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK 0x2074
2375 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
2376 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK 0x207c
2377 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK 0x2080
2378 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK 0x2084
2379 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI 0x2088
2380 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK 0x208c
2381 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI 0x2090
2382 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK 0x2094
2383 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI 0x2098
2384 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK 0x209c
2385 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI 0x20a0
2386 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK 0x20a4
2387 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI 0x20a8
2388 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK 0x20ac
2389 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI 0x20b0
2390 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK 0x20b4
2391 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI 0x20b8
2392 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK 0x20bc
2393 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI 0x20c0
2394 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK 0x20c4
2395 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI 0x20c8
2396 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK 0x20cc
2397 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI 0x20d0
2398 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x20d4
2564 21, CLK_IS_CRITICAL, 0),
2569 21, 0, 0),
2574 21, CLK_IS_CRITICAL, 0),
2578 21, CLK_IS_CRITICAL, 0),
2582 21, CLK_IS_CRITICAL, 0),
2586 21, CLK_IGNORE_UNUSED, 0),
2590 21, 0, 0),
2594 21, 0, 0),
2598 21, 0, 0),
2602 21, 0, 0),
2606 21, CLK_IS_CRITICAL, 0),
2610 21, 0, 0),
2615 21, 0, 0),
2619 21, 0, 0),
2623 21, 0, 0),
2627 21, 0, 0),
2631 21, 0, 0),
2635 21, 0, 0),
2639 21, 0, 0),
2643 21, 0, 0),
2647 21, 0, 0),
2651 21, 0, 0),
2655 21, 0, 0),
2659 21, 0, 0),
2663 21, 0, 0),
2667 21, 0, 0),
2671 21, 0, 0),
2674 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK, 21, 0, 0),
2677 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK, 21, 0, 0),
2681 21, 0, 0),
2684 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK, 21, 0, 0),
2688 21, 0, 0),
2691 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK, 21, 0, 0),
2695 21, 0, 0),
2698 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK, 21, 0, 0),
2702 21, 0, 0),
2705 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK, 21, 0, 0),
2709 21, 0, 0),
2712 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK, 21, 0, 0),
2716 21, 0, 0),
2719 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK, 21, 0, 0),
2723 21, 0, 0),
2726 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK, 21, 0, 0),
2730 21, 0, 0),
2733 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK, 21, 0, 0),
2737 21, 0, 0),
2740 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK, 21, 0, 0),
2744 21, 0, 0),
2748 21, CLK_IGNORE_UNUSED, 0),
2770 return 0; in exynos8895_cmu_probe()