Lines Matching +full:0 +full:x11c00000
37 /* Register Offset definitions for CMU_TOP (0x120e0000) */
38 #define PLL_LOCKTIME_PLL_MMC 0x0000
39 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
40 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
41 #define PLL_CON0_PLL_MMC 0x0100
42 #define PLL_CON3_PLL_MMC 0x010c
43 #define PLL_CON0_PLL_SHARED0 0x0140
44 #define PLL_CON3_PLL_SHARED0 0x014c
45 #define PLL_CON0_PLL_SHARED1 0x0180
46 #define PLL_CON3_PLL_SHARED1 0x018c
47 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
48 #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
49 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
50 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
51 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
52 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
53 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024
54 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028
55 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG 0x102c
56 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1030
57 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
58 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
59 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
60 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
61 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
62 #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
63 #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
64 #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
65 #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
66 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
67 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
68 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
69 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
70 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
71 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
72 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
73 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
74 #define CLK_CON_DIV_CLKCMU_AUD 0x1810
75 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
76 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
77 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
78 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
79 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1830
80 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1834
81 #define CLK_CON_DIV_CLKCMU_CPUCL1_DBG 0x1838
82 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
83 #define CLK_CON_DIV_CLKCMU_DPU 0x1840
84 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
85 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
86 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
87 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
88 #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
89 #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
90 #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
91 #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
92 #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
93 #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
94 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
95 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
96 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
97 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
98 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
99 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
100 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
101 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
102 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
103 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
104 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
105 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
106 #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
107 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
108 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
109 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
110 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
111 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c
112 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030
113 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG 0x2034
114 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2038
115 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
116 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
117 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
118 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
119 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
120 #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
121 #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
122 #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
123 #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
124 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
125 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
126 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
127 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
128 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
129 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
130 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
322 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
326 CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
330 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
332 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
334 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
336 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
340 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
342 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
346 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG, 0, 1),
348 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
352 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
356 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
360 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
362 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
364 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
368 CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
370 CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
372 CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
374 CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
378 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
380 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
382 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
384 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
388 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
390 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
392 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
398 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
400 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
402 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
404 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
406 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
408 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
412 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
416 CLK_CON_DIV_CLKCMU_AUD, 0, 4),
420 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
422 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
424 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
426 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
430 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
432 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
436 CLK_CON_DIV_CLKCMU_CPUCL1_DBG, 0, 3),
438 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
442 CLK_CON_DIV_CLKCMU_DPU, 0, 4),
446 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
450 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
452 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
454 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
458 CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
460 CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
462 CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
464 CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
468 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
470 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
472 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
474 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
478 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
480 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
482 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
488 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
490 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
492 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
494 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
498 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
502 CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
506 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
508 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
512 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG, 21, 0, 0),
514 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
518 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
522 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
526 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
528 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
530 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
535 CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
537 CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
539 CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
541 CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
546 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
548 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
550 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
552 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
556 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
558 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
560 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
588 /* Register Offset definitions for CMU_APM (0x11800000) */
589 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
590 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
591 #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
592 #define PLL_CON0_MUX_DLL_USER 0x0630
593 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
594 #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
595 #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
596 #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
597 #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
598 #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
599 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
600 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
601 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
602 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
603 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
604 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
605 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
606 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
607 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
608 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
644 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
645 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
646 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
647 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
660 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
662 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
664 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
670 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
672 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
674 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
679 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_SET_RATE_PARENT, 0),
682 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
684 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
686 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
688 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
690 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
692 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
696 0),
698 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),
700 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
720 #define PLL_LOCKTIME_PLL_AUD 0x0000
721 #define PLL_CON0_PLL_AUD 0x0100
722 #define PLL_CON3_PLL_AUD 0x010c
723 #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
724 #define PLL_CON0_MUX_TICK_USB_USER 0x0610
725 #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
726 #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
727 #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
728 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
729 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
730 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
731 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
732 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
733 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
734 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
735 #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
736 #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
737 #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
738 #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
739 #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
740 #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
741 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
742 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
743 #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
744 #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
745 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
746 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
747 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
748 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
749 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
750 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
751 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
752 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
753 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
754 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
755 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
756 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
757 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
758 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
759 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
760 #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020
761 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
762 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
763 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
764 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
765 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
766 #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
767 #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
768 #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
769 #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
770 #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
771 #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
772 #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
773 #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
857 FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
858 FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
859 FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
860 FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
861 FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
862 FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
863 FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
864 FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
876 CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
878 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
880 CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
882 CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
884 CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
886 CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
888 CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
890 CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
892 CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
894 CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
899 CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
901 CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
903 CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
905 CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
907 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
910 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
912 CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
914 CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
916 CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
918 CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
920 CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
922 CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
924 CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
926 CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
928 CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
930 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
932 CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
938 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0),
940 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
942 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
944 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
947 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
949 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
951 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
953 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
955 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
957 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
959 CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
961 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
963 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
965 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
967 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
969 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
971 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
973 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
975 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
977 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
979 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
981 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
1003 /* Register Offset definitions for CMU_CMGP (0x11c00000) */
1004 #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
1005 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
1006 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
1007 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
1008 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
1009 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
1010 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
1011 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
1012 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
1013 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
1014 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
1015 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
1016 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
1017 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
1042 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
1047 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
1049 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1, CLK_SET_RATE_PARENT, 0),
1051 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1, CLK_SET_RATE_PARENT, 0),
1056 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
1058 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0),
1060 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5, CLK_SET_RATE_PARENT, 0),
1066 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
1069 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
1073 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1075 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1078 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
1080 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1083 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
1086 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
1106 /* Register Offset definitions for CMU_CPUCL0 (0x10900000) */
1107 #define PLL_LOCKTIME_PLL_CPUCL0 0x0000
1108 #define PLL_CON0_PLL_CPUCL0 0x0100
1109 #define PLL_CON1_PLL_CPUCL0 0x0104
1110 #define PLL_CON3_PLL_CPUCL0 0x010c
1111 #define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0600
1112 #define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0610
1113 #define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x100c
1114 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
1115 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1808
1116 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x180c
1117 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
1118 #define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x1814
1119 #define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1818
1120 #define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x181c
1121 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK 0x2000
1122 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK 0x2004
1123 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK 0x2008
1124 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK 0x200c
1125 #define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK 0x2010
1126 #define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU 0x2020
1159 PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
1160 PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
1161 PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
1162 PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
1163 PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
1164 PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
1165 PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
1166 PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
1188 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
1192 CLK_SET_RATE_PARENT, 0),
1197 CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
1202 CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 1,
1205 CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3,
1208 CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4,
1213 CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4,
1216 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4,
1219 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4,
1222 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4,
1229 CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1233 CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 21, CLK_IGNORE_UNUSED, 0),
1235 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK, 21, CLK_IGNORE_UNUSED, 0),
1238 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
1242 CLK_IGNORE_UNUSED, 0),
1245 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1251 * parameters must be in the range of 0..15, as the divider range for all of
1280 { 0 }
1285 CLK_MOUT_CPUCL0_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL0,
1318 /* Register Offset definitions for CMU_CPUCL1 (0x10800000) */
1319 #define PLL_LOCKTIME_PLL_CPUCL1 0x0000
1320 #define PLL_CON0_PLL_CPUCL1 0x0100
1321 #define PLL_CON1_PLL_CPUCL1 0x0104
1322 #define PLL_CON3_PLL_CPUCL1 0x010c
1323 #define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER 0x0600
1324 #define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
1325 #define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000
1326 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
1327 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1808
1328 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG 0x180c
1329 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
1330 #define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x1814
1331 #define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1818
1332 #define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x181c
1333 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK 0x2000
1334 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK 0x2004
1335 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK 0x2008
1336 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK 0x200c
1337 #define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK 0x2010
1338 #define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU 0x2020
1378 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
1382 CLK_SET_RATE_PARENT, 0),
1387 CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
1392 CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0, 1,
1395 CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 3,
1398 CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4,
1403 CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4,
1406 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4,
1409 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0, 4,
1412 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4,
1419 CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1423 CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 21, CLK_IGNORE_UNUSED, 0),
1425 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK, 21, CLK_IGNORE_UNUSED, 0),
1428 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
1432 CLK_IGNORE_UNUSED, 0),
1435 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1440 CLK_MOUT_CPUCL1_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL1,
1473 /* Register Offset definitions for CMU_G3D (0x11400000) */
1474 #define PLL_LOCKTIME_PLL_G3D 0x0000
1475 #define PLL_CON0_PLL_G3D 0x0100
1476 #define PLL_CON3_PLL_G3D 0x010c
1477 #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
1478 #define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
1479 #define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
1480 #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
1481 #define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
1482 #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
1483 #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
1484 #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
1485 #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
1486 #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
1525 CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
1530 CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
1536 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1538 CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
1540 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
1543 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
1545 CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
1547 CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
1549 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
1569 /* Register Offset definitions for CMU_HSI (0x13400000) */
1570 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
1571 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
1572 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
1573 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
1574 #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000
1575 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
1576 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
1577 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
1578 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
1579 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
1580 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
1581 #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c
1582 #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030
1583 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
1584 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
1585 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
1617 4, 1, CLK_SET_RATE_PARENT, 0),
1622 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
1629 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1631 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
1633 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
1635 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
1638 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1640 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
1643 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
1645 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0),
1647 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0),
1650 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
1652 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
1655 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
1671 #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
1672 #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
1673 #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
1674 #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
1675 #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
1676 #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
1677 #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
1678 #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
1679 #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
1680 #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
1681 #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
1682 #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
1683 #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
1684 #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
1685 #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
1686 #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
1687 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
1688 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
1689 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
1690 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
1691 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
1692 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
1693 #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
1740 CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
1746 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1748 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
1750 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
1752 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
1754 CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
1757 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
1759 CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
1761 CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
1763 CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
1765 CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
1767 CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
1770 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
1772 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
1775 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
1777 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
1780 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
1783 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
1785 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
1803 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
1804 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
1805 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
1806 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
1807 #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
1808 #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
1809 #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
1810 #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
1811 #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
1812 #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
1813 #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
1814 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
1815 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
1816 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
1817 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
1860 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
1867 21, CLK_IGNORE_UNUSED, 0),
1870 21, 0, 0),
1873 21, 0, 0),
1876 21, 0, 0),
1879 21, 0, 0),
1882 21, 0, 0),
1885 21, 0, 0),
1888 21, 0, 0),
1891 21, 0, 0),
1894 21, 0, 0),
1912 /* Register Offset definitions for CMU_PERI (0x10030000) */
1913 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
1914 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
1915 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620
1916 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
1917 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800
1918 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804
1919 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808
1920 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c
1921 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
1922 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
1923 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
1924 #define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK 0x2018
1925 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
1926 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
1927 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
1928 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
1929 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030
1930 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
1931 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038
1932 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c
1933 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040
1934 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044
1935 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048
1936 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c
1937 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050
1938 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054
1939 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c
1940 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064
1941 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c
1942 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0
1943 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4
1944 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
1945 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
1946 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0
1947 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4
2002 CLK_SET_RATE_PARENT, 0),
2007 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
2009 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
2011 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
2013 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5, CLK_SET_RATE_PARENT, 0),
2018 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
2020 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
2022 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
2024 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
2026 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
2028 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
2030 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
2032 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
2034 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
2036 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
2038 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
2040 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
2042 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
2044 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
2046 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
2048 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
2050 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
2053 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
2055 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
2057 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
2060 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
2062 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
2064 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
2066 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
2068 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
2072 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2075 CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, 21, 0, 0),
2102 /* Register Offset definitions for CMU_CORE (0x12000000) */
2103 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
2104 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610
2105 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
2106 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630
2107 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
2108 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
2109 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
2110 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
2111 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
2112 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
2113 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
2114 #define CLK_CON_GAT_GOUT_CORE_PDMA_ACLK 0x20f0
2115 #define CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK 0x2124
2116 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
2117 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
2118 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
2153 4, 1, CLK_SET_RATE_PARENT, 0),
2157 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
2162 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
2168 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
2171 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
2173 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
2176 21, CLK_SET_RATE_PARENT, 0),
2178 "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, 21, 0, 0),
2180 "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, 21, 0, 0),
2182 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
2184 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
2187 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2190 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
2208 /* Register Offset definitions for CMU_DPU (0x13000000) */
2209 #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600
2210 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
2211 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004
2212 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010
2213 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014
2214 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018
2215 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028
2216 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c
2217 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038
2218 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c
2243 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
2250 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2252 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
2254 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
2256 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
2258 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
2260 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
2262 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
2264 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
2290 return 0; in exynos850_cmu_probe()