Lines Matching +full:0 +full:x13400000
27 /* Register Offset definitions for CMU_TOP (0x12060000) */
28 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
29 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
30 #define PLL_CON0_PLL_SHARED0 0x0100
31 #define PLL_CON0_PLL_SHARED1 0x0120
32 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
33 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
34 #define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
35 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028
36 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c
37 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1030
38 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO 0x1034
39 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD 0x1038
40 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058
41 #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c
42 #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060
43 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064
44 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068
45 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c
46 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070
47 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074
48 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078
49 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
50 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820
51 #define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824
52 #define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844
53 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848
54 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c
55 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO 0x1850
56 #define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD 0x1854
57 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874
58 #define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878
59 #define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c
60 #define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880
61 #define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884
62 #define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888
63 #define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c
64 #define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890
65 #define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894
66 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c
67 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0
68 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4
69 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8
70 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac
71 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0
72 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4
73 #define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004
74 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
75 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
76 #define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024
77 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044
78 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048
79 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c
80 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO 0x2050
81 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD 0x2054
82 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c
83 #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080
84 #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084
85 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088
86 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c
87 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090
88 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094
89 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098
204 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
206 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
208 CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
212 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
214 CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1),
216 CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1),
218 CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1),
220 CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1),
222 CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1),
224 CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1),
226 CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
228 CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
232 CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1),
234 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1),
236 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1),
238 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1),
240 CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1),
246 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
248 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
250 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
252 CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
254 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
256 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
258 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
262 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3),
264 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3),
266 CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3),
270 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
272 CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6),
274 CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6),
276 CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4),
278 CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4),
280 CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4),
282 CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4),
284 CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
286 CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
290 CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
292 CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9),
294 CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9),
296 CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9),
298 CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4),
304 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
306 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
308 CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0),
312 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
314 CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0),
316 CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0),
318 CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0),
320 CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0),
322 CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0),
324 CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0),
326 CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
328 CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
332 CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0),
334 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0),
336 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0),
338 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0),
340 CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0),
368 /* Register Offset definitions for CMU_PERI (0x10010000) */
369 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100
370 #define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120
371 #define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140
372 #define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160
373 #define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180
374 #define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0
375 #define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0
376 #define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0
377 #define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200
378 #define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024
379 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
380 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c
381 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030
382 #define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034
383 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038
384 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c
385 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040
386 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044
387 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048
388 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c
389 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050
390 #define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054
391 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058
392 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c
393 #define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060
394 #define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064
395 #define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068
396 #define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c
397 #define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070
398 #define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074
399 #define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078
400 #define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c
401 #define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080
402 #define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084
403 #define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088
404 #define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c
405 #define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090
406 #define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094
407 #define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098
408 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0
409 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0
410 #define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4
411 #define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8
495 CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
497 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
499 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
501 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
503 CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0),
505 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
507 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
509 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
511 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
513 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
515 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
517 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
519 CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0),
522 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
524 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
526 CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0),
528 CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0),
530 CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0),
532 CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0),
534 CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0),
536 CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0),
538 CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0),
540 CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0),
542 CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0),
544 CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0),
546 CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0),
548 CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0),
550 CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0),
552 CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0),
554 CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0),
556 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
559 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
561 CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0),
563 CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0),
588 /* Register Offset definitions for CMU_CORE (0x12000000) */
589 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100
590 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120
591 #define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140
592 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
593 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
594 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054
595 #define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058
596 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK 0x215c
597 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK 0x2160
598 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK 0x2164
599 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE 0x2168
600 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE 0x216c
601 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK 0x2170
602 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE 0x2174
635 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
640 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
646 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
649 CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
655 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0),
657 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0),
659 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
662 CLK_IS_CRITICAL, 0),
665 CLK_IS_CRITICAL, 0),
667 CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
670 CLK_IS_CRITICAL, 0),
688 /* Register Offset definitions for CMU_FSYS (0x13400000) */
689 #define PLL_LOCKTIME_PLL_USB 0x0000
690 #define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
691 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
692 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
693 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
694 #define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
695 #define PLL_CON0_PLL_USB 0x01a0
696 #define CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE 0x200c
697 #define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
698 #define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
699 #define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
700 #define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
701 #define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
702 #define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
703 #define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL 0x2068
704 #define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0 0x206c
705 #define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1 0x2070
706 #define CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY 0x2074
707 #define CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK 0x2078
754 4, 1, CLK_SET_RATE_PARENT, 0),
757 4, 1, CLK_SET_RATE_PARENT, 0),
760 4, 1, CLK_SET_RATE_PARENT, 0),
765 PLL_CON0_PLL_USB, 4, 1, CLK_SET_RATE_PARENT, 0),
770 CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE, 21, CLK_SET_RATE_PARENT, 0),
772 CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
775 21, CLK_SET_RATE_PARENT, 0),
777 CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0),
780 21, CLK_SET_RATE_PARENT, 0),
782 CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0),
785 21, CLK_SET_RATE_PARENT, 0),
787 "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL, 21, 0, 0),
789 "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0, 21, 0, 0),
791 "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1, 21, 0, 0),
793 "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY, 21, 0, 0),
795 CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK, 21, 0, 0),
821 return 0; in exynos7885_cmu_probe()