Lines Matching +full:0 +full:x0900
12 /* Register Offset definitions for CMU_TOPC (0x10570000) */
13 #define CC_PLL_LOCK 0x0000
14 #define BUS0_PLL_LOCK 0x0004
15 #define BUS1_DPLL_LOCK 0x0008
16 #define MFC_PLL_LOCK 0x000C
17 #define AUD_PLL_LOCK 0x0010
18 #define CC_PLL_CON0 0x0100
19 #define BUS0_PLL_CON0 0x0110
20 #define BUS1_DPLL_CON0 0x0120
21 #define MFC_PLL_CON0 0x0130
22 #define AUD_PLL_CON0 0x0140
23 #define MUX_SEL_TOPC0 0x0200
24 #define MUX_SEL_TOPC1 0x0204
25 #define MUX_SEL_TOPC2 0x0208
26 #define MUX_SEL_TOPC3 0x020C
27 #define DIV_TOPC0 0x0600
28 #define DIV_TOPC1 0x0604
29 #define DIV_TOPC3 0x060C
30 #define ENABLE_ACLK_TOPC0 0x0800
31 #define ENABLE_ACLK_TOPC1 0x0804
32 #define ENABLE_SCLK_TOPC1 0x0A04
35 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
36 FFACTOR(0, "ffac_topc_bus0_pll_div4",
37 "ffac_topc_bus0_pll_div2", 1, 2, 0),
38 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
39 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
40 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
88 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
89 MUX_SEL_TOPC0, 0, 1),
90 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
92 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
94 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
96 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
98 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
100 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
102 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
105 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
106 MUX_SEL_TOPC1, 0, 1),
107 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
110 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
112 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
113 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
126 DIV_TOPC3, 0, 4),
138 PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),
144 ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
147 ENABLE_ACLK_TOPC1, 20, 0, 0),
150 ENABLE_ACLK_TOPC1, 24, 0, 0),
153 ENABLE_SCLK_TOPC1, 20, 0, 0),
155 ENABLE_SCLK_TOPC1, 17, 0, 0),
157 ENABLE_SCLK_TOPC1, 16, 0, 0),
159 ENABLE_SCLK_TOPC1, 13, 0, 0),
161 ENABLE_SCLK_TOPC1, 12, 0, 0),
163 ENABLE_SCLK_TOPC1, 5, 0, 0),
165 ENABLE_SCLK_TOPC1, 4, 0, 0),
167 ENABLE_SCLK_TOPC1, 1, 0, 0),
169 ENABLE_SCLK_TOPC1, 0, 0, 0),
173 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
175 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
177 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
179 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
209 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */
210 #define MUX_SEL_TOP00 0x0200
211 #define MUX_SEL_TOP01 0x0204
212 #define MUX_SEL_TOP03 0x020C
213 #define MUX_SEL_TOP0_PERIC0 0x0230
214 #define MUX_SEL_TOP0_PERIC1 0x0234
215 #define MUX_SEL_TOP0_PERIC2 0x0238
216 #define MUX_SEL_TOP0_PERIC3 0x023C
217 #define DIV_TOP03 0x060C
218 #define DIV_TOP0_PERIC0 0x0630
219 #define DIV_TOP0_PERIC1 0x0634
220 #define DIV_TOP0_PERIC2 0x0638
221 #define DIV_TOP0_PERIC3 0x063C
222 #define ENABLE_ACLK_TOP03 0x080C
223 #define ENABLE_SCLK_TOP0_PERIC0 0x0A30
224 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34
225 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38
226 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
274 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
275 MUX_SEL_TOP00, 0, 1),
276 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
278 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
280 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
282 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
285 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
287 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
289 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
291 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
294 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
295 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
297 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
298 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
299 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
301 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
302 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
304 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
305 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
306 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
307 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
308 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
309 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
310 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
319 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
320 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
321 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
323 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
324 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
326 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
327 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
329 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
330 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
331 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
332 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
333 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
338 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
340 ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
343 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
345 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
347 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
350 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
352 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
355 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
357 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
359 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
361 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
363 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
365 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
367 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
371 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
372 1, 2, 0),
373 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
374 1, 2, 0),
375 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
376 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
401 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */
402 #define MUX_SEL_TOP10 0x0200
403 #define MUX_SEL_TOP11 0x0204
404 #define MUX_SEL_TOP13 0x020C
405 #define MUX_SEL_TOP1_FSYS0 0x0224
406 #define MUX_SEL_TOP1_FSYS1 0x0228
407 #define MUX_SEL_TOP1_FSYS11 0x022C
408 #define DIV_TOP13 0x060C
409 #define DIV_TOP1_FSYS0 0x0624
410 #define DIV_TOP1_FSYS1 0x0628
411 #define DIV_TOP1_FSYS11 0x062C
412 #define ENABLE_ACLK_TOP13 0x080C
413 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24
414 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28
415 #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
454 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
456 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
458 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
460 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
463 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
465 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
467 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
469 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
472 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
473 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
475 MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
476 MUX_SEL_TOP1_FSYS0, 0, 2),
477 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
478 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
481 MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
482 MUX_SEL_TOP1_FSYS1, 0, 2),
483 MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
486 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
487 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
488 MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
499 "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
507 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
511 DIV_TOP1_FSYS11, 0, 10),
521 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
522 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
523 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
526 ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
529 ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
532 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
534 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
538 CLK_IS_CRITICAL, 0),
545 CLK_IS_CRITICAL, 0),
549 24, CLK_SET_RATE_PARENT, 0),
553 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
554 1, 2, 0),
555 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
556 1, 2, 0),
557 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
558 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
583 /* Register Offset definitions for CMU_CCORE (0x105B0000) */
584 #define MUX_SEL_CCORE 0x0200
585 #define DIV_CCORE 0x0600
586 #define ENABLE_ACLK_CCORE0 0x0800
587 #define ENABLE_ACLK_CCORE1 0x0804
588 #define ENABLE_PCLK_CCORE 0x0900
601 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
607 ENABLE_PCLK_CCORE, 8, 0, 0),
628 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
629 #define MUX_SEL_PERIC0 0x0200
630 #define ENABLE_PCLK_PERIC0 0x0900
631 #define ENABLE_SCLK_PERIC0 0x0A00
644 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
645 MUX_SEL_PERIC0, 0, 1),
646 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
652 ENABLE_PCLK_PERIC0, 8, 0, 0),
654 ENABLE_PCLK_PERIC0, 9, 0, 0),
656 ENABLE_PCLK_PERIC0, 10, 0, 0),
658 ENABLE_PCLK_PERIC0, 11, 0, 0),
660 ENABLE_PCLK_PERIC0, 12, 0, 0),
662 ENABLE_PCLK_PERIC0, 13, 0, 0),
664 ENABLE_PCLK_PERIC0, 14, 0, 0),
666 ENABLE_PCLK_PERIC0, 16, 0, 0),
668 ENABLE_PCLK_PERIC0, 20, 0, 0),
670 ENABLE_PCLK_PERIC0, 21, 0, 0),
673 ENABLE_SCLK_PERIC0, 16, 0, 0),
674 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
692 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
693 #define MUX_SEL_PERIC10 0x0200
694 #define MUX_SEL_PERIC11 0x0204
695 #define MUX_SEL_PERIC12 0x0208
696 #define ENABLE_PCLK_PERIC1 0x0900
697 #define ENABLE_SCLK_PERIC10 0x0A00
722 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
723 MUX_SEL_PERIC10, 0, 1),
725 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
726 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
727 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
728 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
729 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
730 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
731 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
732 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
733 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
734 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
735 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
737 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
739 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
745 ENABLE_PCLK_PERIC1, 4, 0, 0),
747 ENABLE_PCLK_PERIC1, 5, 0, 0),
749 ENABLE_PCLK_PERIC1, 6, 0, 0),
751 ENABLE_PCLK_PERIC1, 7, 0, 0),
753 ENABLE_PCLK_PERIC1, 8, 0, 0),
755 ENABLE_PCLK_PERIC1, 9, 0, 0),
757 ENABLE_PCLK_PERIC1, 10, 0, 0),
759 ENABLE_PCLK_PERIC1, 11, 0, 0),
761 ENABLE_PCLK_PERIC1, 12, 0, 0),
763 ENABLE_PCLK_PERIC1, 13, 0, 0),
765 ENABLE_PCLK_PERIC1, 14, 0, 0),
767 ENABLE_PCLK_PERIC1, 15, 0, 0),
769 ENABLE_PCLK_PERIC1, 16, 0, 0),
771 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
773 ENABLE_PCLK_PERIC1, 18, 0, 0),
775 ENABLE_PCLK_PERIC1, 19, 0, 0),
778 ENABLE_SCLK_PERIC10, 9, 0, 0),
780 ENABLE_SCLK_PERIC10, 10, 0, 0),
782 ENABLE_SCLK_PERIC10, 11, 0, 0),
784 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
786 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
788 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
790 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
792 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
794 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
796 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
798 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
819 /* Register Offset definitions for CMU_PERIS (0x10040000) */
820 #define MUX_SEL_PERIS 0x0200
821 #define ENABLE_PCLK_PERIS 0x0900
822 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
823 #define ENABLE_SCLK_PERIS 0x0A00
824 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
838 MUX(0, "mout_aclk_peris_66_user",
839 mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
844 ENABLE_PCLK_PERIS, 6, 0, 0),
846 ENABLE_PCLK_PERIS, 10, 0, 0),
849 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
851 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
853 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
874 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
875 #define MUX_SEL_FSYS00 0x0200
876 #define MUX_SEL_FSYS01 0x0204
877 #define MUX_SEL_FSYS02 0x0208
878 #define ENABLE_ACLK_FSYS00 0x0800
879 #define ENABLE_ACLK_FSYS01 0x0804
880 #define ENABLE_SCLK_FSYS01 0x0A04
881 #define ENABLE_SCLK_FSYS02 0x0A08
882 #define ENABLE_SCLK_FSYS04 0x0A10
898 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
899 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
914 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
917 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
919 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
922 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
925 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
932 ENABLE_ACLK_FSYS00, 3, 0, 0),
934 ENABLE_ACLK_FSYS00, 4, 0, 0),
937 ENABLE_ACLK_FSYS00, 19, 0, 0),
940 ENABLE_ACLK_FSYS01, 29, 0, 0),
942 ENABLE_ACLK_FSYS01, 31, 0, 0),
946 ENABLE_SCLK_FSYS01, 4, 0, 0),
948 ENABLE_SCLK_FSYS01, 8, 0, 0),
953 ENABLE_SCLK_FSYS02, 24, 0, 0),
957 ENABLE_SCLK_FSYS02, 28, 0, 0),
961 ENABLE_SCLK_FSYS04, 28, 0, 0),
984 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
985 #define MUX_SEL_FSYS10 0x0200
986 #define MUX_SEL_FSYS11 0x0204
987 #define MUX_SEL_FSYS12 0x0208
988 #define DIV_FSYS1 0x0600
989 #define ENABLE_ACLK_FSYS1 0x0800
990 #define ENABLE_PCLK_FSYS1 0x0900
991 #define ENABLE_SCLK_FSYS11 0x0A04
992 #define ENABLE_SCLK_FSYS12 0x0A08
993 #define ENABLE_SCLK_FSYS13 0x0A0C
1011 0, 300000000),
1013 0, 300000000),
1015 0, 300000000),
1033 MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
1035 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
1038 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
1040 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
1042 MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
1045 MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
1047 MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
1049 MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
1055 DIV_FSYS1, 0, 2),
1061 ENABLE_SCLK_FSYS11, 20, 0, 0),
1064 ENABLE_ACLK_FSYS1, 29, 0, 0),
1066 ENABLE_ACLK_FSYS1, 30, 0, 0),
1069 ENABLE_ACLK_FSYS1, 31, 0, 0),
1071 ENABLE_PCLK_FSYS1, 30, 0, 0),
1075 ENABLE_SCLK_FSYS12, 16, 0, 0),
1078 ENABLE_SCLK_FSYS12, 24, 0, 0),
1081 ENABLE_SCLK_FSYS12, 28, 0, 0),
1086 ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
1090 ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
1115 #define MUX_SEL_MSCL 0x0200
1116 #define DIV_MSCL 0x0600
1117 #define ENABLE_ACLK_MSCL 0x0800
1118 #define ENABLE_PCLK_MSCL 0x0900
1132 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
1136 DIV_MSCL, 0, 3),
1141 ENABLE_ACLK_MSCL, 31, 0, 0),
1143 ENABLE_ACLK_MSCL, 30, 0, 0),
1145 ENABLE_ACLK_MSCL, 29, 0, 0),
1147 ENABLE_ACLK_MSCL, 28, 0, 0),
1150 ENABLE_ACLK_MSCL, 27, 0, 0),
1153 ENABLE_ACLK_MSCL, 26, 0, 0),
1155 ENABLE_ACLK_MSCL, 25, 0, 0),
1157 ENABLE_ACLK_MSCL, 24, 0, 0),
1160 ENABLE_ACLK_MSCL, 23, 0, 0),
1162 ENABLE_ACLK_MSCL, 22, 0, 0),
1164 ENABLE_ACLK_MSCL, 21, 0, 0),
1166 ENABLE_ACLK_MSCL, 20, 0, 0),
1168 ENABLE_ACLK_MSCL, 19, 0, 0),
1170 ENABLE_ACLK_MSCL, 18, 0, 0),
1172 ENABLE_ACLK_MSCL, 17, 0, 0),
1174 ENABLE_ACLK_MSCL, 16, 0, 0),
1177 ENABLE_ACLK_MSCL, 15, 0, 0),
1180 ENABLE_ACLK_MSCL, 14, 0, 0),
1183 ENABLE_PCLK_MSCL, 31, 0, 0),
1185 ENABLE_PCLK_MSCL, 30, 0, 0),
1187 ENABLE_PCLK_MSCL, 29, 0, 0),
1189 ENABLE_PCLK_MSCL, 28, 0, 0),
1191 ENABLE_PCLK_MSCL, 27, 0, 0),
1193 ENABLE_PCLK_MSCL, 26, 0, 0),
1195 ENABLE_PCLK_MSCL, 25, 0, 0),
1197 ENABLE_PCLK_MSCL, 24, 0, 0),
1199 ENABLE_PCLK_MSCL, 23, 0, 0),
1201 ENABLE_PCLK_MSCL, 22, 0, 0),
1203 ENABLE_PCLK_MSCL, 21, 0, 0),
1205 ENABLE_PCLK_MSCL, 20, 0, 0),
1228 /* Register Offset definitions for CMU_AUD (0x114C0000) */
1229 #define MUX_SEL_AUD 0x0200
1230 #define DIV_AUD0 0x0600
1231 #define DIV_AUD1 0x0604
1232 #define ENABLE_ACLK_AUD 0x0800
1233 #define ENABLE_PCLK_AUD 0x0900
1234 #define ENABLE_SCLK_AUD 0x0A00
1252 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1253 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1254 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1258 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1259 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1260 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
1262 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
1263 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
1264 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
1265 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
1266 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1271 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1273 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
1274 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
1275 GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1276 ENABLE_SCLK_AUD, 30, 0, 0),
1278 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
1279 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
1280 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
1281 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
1282 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
1283 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
1285 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
1287 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1288 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
1289 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
1291 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
1292 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
1293 ENABLE_ACLK_AUD, 28, 0, 0),
1294 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),