Lines Matching refs:ENABLE_PCLK_PERIC0
1575 #define ENABLE_PCLK_PERIC0 0x0900 macro
1585 ENABLE_PCLK_PERIC0,
1595 { ENABLE_PCLK_PERIC0, 0xe00ff000 },
1618 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1621 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1623 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1624 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1626 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1628 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1630 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1632 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1634 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1636 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1638 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1641 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1643 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1645 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1647 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1649 ENABLE_PCLK_PERIC0, 15,
1651 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1653 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1655 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1658 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1660 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1662 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1664 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1665 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1667 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1669 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1671 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1673 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1675 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1677 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1679 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,