Lines Matching +full:0 +full:x0900
48 #define ISP_PLL_LOCK 0x0000
49 #define AUD_PLL_LOCK 0x0004
50 #define ISP_PLL_CON0 0x0100
51 #define ISP_PLL_CON1 0x0104
52 #define ISP_PLL_FREQ_DET 0x0108
53 #define AUD_PLL_CON0 0x0110
54 #define AUD_PLL_CON1 0x0114
55 #define AUD_PLL_CON2 0x0118
56 #define AUD_PLL_FREQ_DET 0x011c
57 #define MUX_SEL_TOP0 0x0200
58 #define MUX_SEL_TOP1 0x0204
59 #define MUX_SEL_TOP2 0x0208
60 #define MUX_SEL_TOP3 0x020c
61 #define MUX_SEL_TOP4 0x0210
62 #define MUX_SEL_TOP_MSCL 0x0220
63 #define MUX_SEL_TOP_CAM1 0x0224
64 #define MUX_SEL_TOP_DISP 0x0228
65 #define MUX_SEL_TOP_FSYS0 0x0230
66 #define MUX_SEL_TOP_FSYS1 0x0234
67 #define MUX_SEL_TOP_PERIC0 0x0238
68 #define MUX_SEL_TOP_PERIC1 0x023c
69 #define MUX_ENABLE_TOP0 0x0300
70 #define MUX_ENABLE_TOP1 0x0304
71 #define MUX_ENABLE_TOP2 0x0308
72 #define MUX_ENABLE_TOP3 0x030c
73 #define MUX_ENABLE_TOP4 0x0310
74 #define MUX_ENABLE_TOP_MSCL 0x0320
75 #define MUX_ENABLE_TOP_CAM1 0x0324
76 #define MUX_ENABLE_TOP_DISP 0x0328
77 #define MUX_ENABLE_TOP_FSYS0 0x0330
78 #define MUX_ENABLE_TOP_FSYS1 0x0334
79 #define MUX_ENABLE_TOP_PERIC0 0x0338
80 #define MUX_ENABLE_TOP_PERIC1 0x033c
81 #define MUX_STAT_TOP0 0x0400
82 #define MUX_STAT_TOP1 0x0404
83 #define MUX_STAT_TOP2 0x0408
84 #define MUX_STAT_TOP3 0x040c
85 #define MUX_STAT_TOP4 0x0410
86 #define MUX_STAT_TOP_MSCL 0x0420
87 #define MUX_STAT_TOP_CAM1 0x0424
88 #define MUX_STAT_TOP_FSYS0 0x0430
89 #define MUX_STAT_TOP_FSYS1 0x0434
90 #define MUX_STAT_TOP_PERIC0 0x0438
91 #define MUX_STAT_TOP_PERIC1 0x043c
92 #define DIV_TOP0 0x0600
93 #define DIV_TOP1 0x0604
94 #define DIV_TOP2 0x0608
95 #define DIV_TOP3 0x060c
96 #define DIV_TOP4 0x0610
97 #define DIV_TOP_MSCL 0x0618
98 #define DIV_TOP_CAM10 0x061c
99 #define DIV_TOP_CAM11 0x0620
100 #define DIV_TOP_FSYS0 0x062c
101 #define DIV_TOP_FSYS1 0x0630
102 #define DIV_TOP_FSYS2 0x0634
103 #define DIV_TOP_PERIC0 0x0638
104 #define DIV_TOP_PERIC1 0x063c
105 #define DIV_TOP_PERIC2 0x0640
106 #define DIV_TOP_PERIC3 0x0644
107 #define DIV_TOP_PERIC4 0x0648
108 #define DIV_TOP_PLL_FREQ_DET 0x064c
109 #define DIV_STAT_TOP0 0x0700
110 #define DIV_STAT_TOP1 0x0704
111 #define DIV_STAT_TOP2 0x0708
112 #define DIV_STAT_TOP3 0x070c
113 #define DIV_STAT_TOP4 0x0710
114 #define DIV_STAT_TOP_MSCL 0x0718
115 #define DIV_STAT_TOP_CAM10 0x071c
116 #define DIV_STAT_TOP_CAM11 0x0720
117 #define DIV_STAT_TOP_FSYS0 0x072c
118 #define DIV_STAT_TOP_FSYS1 0x0730
119 #define DIV_STAT_TOP_FSYS2 0x0734
120 #define DIV_STAT_TOP_PERIC0 0x0738
121 #define DIV_STAT_TOP_PERIC1 0x073c
122 #define DIV_STAT_TOP_PERIC2 0x0740
123 #define DIV_STAT_TOP_PERIC3 0x0744
124 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
125 #define ENABLE_ACLK_TOP 0x0800
126 #define ENABLE_SCLK_TOP 0x0a00
127 #define ENABLE_SCLK_TOP_MSCL 0x0a04
128 #define ENABLE_SCLK_TOP_CAM1 0x0a08
129 #define ENABLE_SCLK_TOP_DISP 0x0a0c
130 #define ENABLE_SCLK_TOP_FSYS 0x0a10
131 #define ENABLE_SCLK_TOP_PERIC 0x0a14
132 #define ENABLE_IP_TOP 0x0b00
133 #define ENABLE_CMU_TOP 0x0c00
134 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
201 { ENABLE_ACLK_TOP, 0x67ecffed },
203 { ENABLE_SCLK_TOP_PERIC, 0x38 },
205 { ISP_PLL_CON0, 0x85cc0502 },
207 { AUD_PLL_CON0, 0x84830202 },
258 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
262 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
263 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
264 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
266 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
267 /* XspiCLK[4:0] input clock for SPI */
268 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
269 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
270 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
271 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
272 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
274 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
282 0, 1),
292 MUX_SEL_TOP1, 0, 1),
306 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
320 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
328 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
336 MUX_SEL_TOP_MSCL, 0, 1),
350 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
368 MUX_SEL_TOP_FSYS0, 0, 1),
378 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
396 MUX_SEL_TOP_PERIC0, 0, 1),
406 MUX_SEL_TOP_PERIC1, 0, 2),
410 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
430 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
444 DIV_TOP1, 0, 3),
450 DIV_TOP2, 0, 3),
466 "mout_bus_pll_user", DIV_TOP3, 0, 3),
474 DIV_TOP4, 0, 3),
478 DIV_TOP_MSCL, 0, 4),
490 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
504 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
512 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
514 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
520 DIV_TOP_FSYS1, 0, 4),
530 DIV_TOP_FSYS2, 0, 4),
540 DIV_TOP_PERIC0, 0, 4),
546 DIV_TOP_PERIC1, 0, 4),
554 DIV_TOP_PERIC2, 0, 4),
564 DIV_TOP_PERIC3, 0, 4),
574 DIV_TOP_PERIC4, 0, 4),
580 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
583 29, CLK_IGNORE_UNUSED, 0),
586 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
589 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
592 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
595 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
598 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
601 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
604 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
607 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
610 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
613 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
616 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
619 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
622 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
625 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
628 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
631 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
634 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
637 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
640 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
643 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
646 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
648 ENABLE_ACLK_TOP, 0,
649 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
653 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
657 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
659 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
661 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
663 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
665 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
667 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
669 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
673 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
674 CLK_IGNORE_UNUSED, 0),
678 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
680 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
682 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
684 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
687 3, CLK_SET_RATE_PARENT, 0),
690 1, CLK_SET_RATE_PARENT, 0),
693 0, CLK_SET_RATE_PARENT, 0),
697 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
699 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
701 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
703 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
705 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
708 CLK_IGNORE_UNUSED, 0),
711 CLK_IGNORE_UNUSED, 0),
714 CLK_IGNORE_UNUSED, 0),
716 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
718 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
720 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
724 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
726 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
728 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
736 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
737 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
738 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
739 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
740 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
741 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
742 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
743 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
744 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
745 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
746 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
747 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
748 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
749 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
789 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
791 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
796 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
797 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
839 #define MPHY_PLL_LOCK 0x0000
840 #define MPHY_PLL_CON0 0x0100
841 #define MPHY_PLL_CON1 0x0104
842 #define MPHY_PLL_FREQ_DET 0x010c
843 #define MUX_SEL_CPIF0 0x0200
844 #define DIV_CPIF 0x0600
845 #define ENABLE_SCLK_CPIF 0x0a00
859 { ENABLE_SCLK_CPIF, 0x3ff },
861 { MPHY_PLL_CON0, 0x81c70601 },
875 0, 1),
881 0, 6),
887 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
889 ENABLE_SCLK_CPIF, 4, 0, 0),
918 #define MEM0_PLL_LOCK 0x0000
919 #define MEM1_PLL_LOCK 0x0004
920 #define BUS_PLL_LOCK 0x0008
921 #define MFC_PLL_LOCK 0x000c
922 #define MEM0_PLL_CON0 0x0100
923 #define MEM0_PLL_CON1 0x0104
924 #define MEM0_PLL_FREQ_DET 0x010c
925 #define MEM1_PLL_CON0 0x0110
926 #define MEM1_PLL_CON1 0x0114
927 #define MEM1_PLL_FREQ_DET 0x011c
928 #define BUS_PLL_CON0 0x0120
929 #define BUS_PLL_CON1 0x0124
930 #define BUS_PLL_FREQ_DET 0x012c
931 #define MFC_PLL_CON0 0x0130
932 #define MFC_PLL_CON1 0x0134
933 #define MFC_PLL_FREQ_DET 0x013c
934 #define MUX_SEL_MIF0 0x0200
935 #define MUX_SEL_MIF1 0x0204
936 #define MUX_SEL_MIF2 0x0208
937 #define MUX_SEL_MIF3 0x020c
938 #define MUX_SEL_MIF4 0x0210
939 #define MUX_SEL_MIF5 0x0214
940 #define MUX_SEL_MIF6 0x0218
941 #define MUX_SEL_MIF7 0x021c
942 #define MUX_ENABLE_MIF0 0x0300
943 #define MUX_ENABLE_MIF1 0x0304
944 #define MUX_ENABLE_MIF2 0x0308
945 #define MUX_ENABLE_MIF3 0x030c
946 #define MUX_ENABLE_MIF4 0x0310
947 #define MUX_ENABLE_MIF5 0x0314
948 #define MUX_ENABLE_MIF6 0x0318
949 #define MUX_ENABLE_MIF7 0x031c
950 #define MUX_STAT_MIF0 0x0400
951 #define MUX_STAT_MIF1 0x0404
952 #define MUX_STAT_MIF2 0x0408
953 #define MUX_STAT_MIF3 0x040c
954 #define MUX_STAT_MIF4 0x0410
955 #define MUX_STAT_MIF5 0x0414
956 #define MUX_STAT_MIF6 0x0418
957 #define MUX_STAT_MIF7 0x041c
958 #define DIV_MIF1 0x0604
959 #define DIV_MIF2 0x0608
960 #define DIV_MIF3 0x060c
961 #define DIV_MIF4 0x0610
962 #define DIV_MIF5 0x0614
963 #define DIV_MIF_PLL_FREQ_DET 0x0618
964 #define DIV_STAT_MIF1 0x0704
965 #define DIV_STAT_MIF2 0x0708
966 #define DIV_STAT_MIF3 0x070c
967 #define DIV_STAT_MIF4 0x0710
968 #define DIV_STAT_MIF5 0x0714
969 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
970 #define ENABLE_ACLK_MIF0 0x0800
971 #define ENABLE_ACLK_MIF1 0x0804
972 #define ENABLE_ACLK_MIF2 0x0808
973 #define ENABLE_ACLK_MIF3 0x080c
974 #define ENABLE_PCLK_MIF 0x0900
975 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
976 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
977 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
978 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
979 #define ENABLE_SCLK_MIF 0x0a00
980 #define ENABLE_IP_MIF0 0x0b00
981 #define ENABLE_IP_MIF1 0x0b04
982 #define ENABLE_IP_MIF2 0x0b08
983 #define ENABLE_IP_MIF3 0x0b0c
984 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
985 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
986 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
987 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
988 #define CLKOUT_CMU_MIF 0x0c00
989 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
990 #define DREX_FREQ_CTRL0 0x1000
991 #define DREX_FREQ_CTRL1 0x1004
992 #define PAUSE 0x1008
993 #define DDRPHY_LOCK_CTRL 0x100c
1123 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1124 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1125 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1126 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1146 0, 1),
1166 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1172 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1186 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1200 MUX_SEL_MIF5, 0, 1),
1208 MUX_SEL_MIF6, 0, 1),
1222 MUX_SEL_MIF7, 0, 1),
1248 DIV_MIF2, 0, 3),
1256 DIV_MIF3, 0, 3),
1272 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1276 0, 3),
1282 19, CLK_IGNORE_UNUSED, 0),
1284 18, CLK_IGNORE_UNUSED, 0),
1286 17, CLK_IGNORE_UNUSED, 0),
1288 16, CLK_IGNORE_UNUSED, 0),
1290 15, CLK_IGNORE_UNUSED, 0),
1292 14, CLK_IGNORE_UNUSED, 0),
1294 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1296 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1298 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1300 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1302 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1304 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1306 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1308 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1310 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1312 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1314 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1316 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1318 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1320 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1325 CLK_IGNORE_UNUSED, 0),
1328 27, CLK_IGNORE_UNUSED, 0),
1331 26, CLK_IGNORE_UNUSED, 0),
1334 25, CLK_IGNORE_UNUSED, 0),
1337 24, CLK_IGNORE_UNUSED, 0),
1340 23, CLK_IGNORE_UNUSED, 0),
1343 22, CLK_IGNORE_UNUSED, 0),
1346 21, CLK_IGNORE_UNUSED, 0),
1349 20, CLK_IGNORE_UNUSED, 0),
1352 19, CLK_IGNORE_UNUSED, 0),
1355 18, CLK_IGNORE_UNUSED, 0),
1358 17, CLK_IGNORE_UNUSED, 0),
1361 16, CLK_IGNORE_UNUSED, 0),
1364 15, CLK_IGNORE_UNUSED, 0),
1367 14, CLK_IGNORE_UNUSED, 0),
1370 13, CLK_IGNORE_UNUSED, 0),
1373 12, CLK_IGNORE_UNUSED, 0),
1376 11, CLK_IGNORE_UNUSED, 0),
1379 10, CLK_IGNORE_UNUSED, 0),
1381 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1383 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1385 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1387 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1389 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1391 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1393 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1395 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1397 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1399 0, CLK_IGNORE_UNUSED, 0),
1403 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1405 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1407 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1409 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1411 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1413 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1415 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1418 CLK_IGNORE_UNUSED, 0),
1421 5, CLK_IGNORE_UNUSED, 0),
1423 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1426 3, CLK_IGNORE_UNUSED, 0),
1428 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1433 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1436 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1438 ENABLE_ACLK_MIF3, 0,
1439 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1443 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1445 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1447 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1449 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1451 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1453 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1456 CLK_IGNORE_UNUSED, 0),
1458 ENABLE_PCLK_MIF, 19, 0, 0),
1460 ENABLE_PCLK_MIF, 18, 0, 0),
1462 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1464 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1466 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1468 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1470 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1472 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1474 ENABLE_PCLK_MIF, 11, 0, 0),
1476 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1478 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1480 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1482 ENABLE_PCLK_MIF, 7, 0, 0),
1484 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1486 ENABLE_PCLK_MIF, 5, 0, 0),
1488 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1490 ENABLE_PCLK_MIF, 2, 0, 0),
1492 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1496 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1497 CLK_IGNORE_UNUSED, 0),
1501 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1502 CLK_IGNORE_UNUSED, 0),
1506 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1510 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1514 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1517 14, CLK_IGNORE_UNUSED, 0),
1519 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1521 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1524 7, CLK_IGNORE_UNUSED, 0),
1527 6, CLK_IGNORE_UNUSED, 0),
1530 5, CLK_IGNORE_UNUSED, 0),
1533 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1535 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1537 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1539 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1541 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1570 #define DIV_PERIC 0x0600
1571 #define DIV_STAT_PERIC 0x0700
1572 #define ENABLE_ACLK_PERIC 0x0800
1573 #define ENABLE_PCLK_PERIC0 0x0900
1574 #define ENABLE_PCLK_PERIC1 0x0904
1575 #define ENABLE_SCLK_PERIC 0x0A00
1576 #define ENABLE_IP_PERIC0 0x0B00
1577 #define ENABLE_IP_PERIC1 0x0B04
1578 #define ENABLE_IP_PERIC2 0x0B08
1592 /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1593 { ENABLE_PCLK_PERIC0, 0xe00ff000 },
1594 /* sclk: uart2-0 */
1595 { ENABLE_SCLK_PERIC, 0x7 },
1601 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1607 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1609 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1611 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1613 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1617 31, CLK_SET_RATE_PARENT, 0),
1619 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1621 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1623 28, CLK_SET_RATE_PARENT, 0),
1625 26, CLK_SET_RATE_PARENT, 0),
1627 25, CLK_SET_RATE_PARENT, 0),
1629 24, CLK_SET_RATE_PARENT, 0),
1631 23, CLK_SET_RATE_PARENT, 0),
1633 22, CLK_SET_RATE_PARENT, 0),
1635 21, CLK_SET_RATE_PARENT, 0),
1637 20, CLK_SET_RATE_PARENT, 0),
1639 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1641 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1643 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1645 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1648 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1650 14, CLK_SET_RATE_PARENT, 0),
1652 13, CLK_SET_RATE_PARENT, 0),
1654 12, CLK_SET_RATE_PARENT, 0),
1656 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1658 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1660 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1662 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1664 7, CLK_SET_RATE_PARENT, 0),
1666 6, CLK_SET_RATE_PARENT, 0),
1668 5, CLK_SET_RATE_PARENT, 0),
1670 4, CLK_SET_RATE_PARENT, 0),
1672 3, CLK_SET_RATE_PARENT, 0),
1674 2, CLK_SET_RATE_PARENT, 0),
1676 1, CLK_SET_RATE_PARENT, 0),
1678 0, CLK_SET_RATE_PARENT, 0),
1682 9, CLK_SET_RATE_PARENT, 0),
1684 8, CLK_SET_RATE_PARENT, 0),
1686 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1688 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1690 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1692 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1694 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1696 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1698 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1700 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1704 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1706 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1708 19, CLK_SET_RATE_PARENT, 0),
1710 18, CLK_SET_RATE_PARENT, 0),
1712 17, 0, 0),
1714 16, 0, 0),
1715 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1717 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1719 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1721 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1724 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1726 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1728 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1731 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1733 5, CLK_SET_RATE_PARENT, 0),
1735 4, CLK_SET_RATE_PARENT, 0),
1737 3, CLK_SET_RATE_PARENT, 0),
1740 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1743 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1745 ENABLE_SCLK_PERIC, 0,
1746 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1772 #define ENABLE_ACLK_PERIS 0x0800
1773 #define ENABLE_PCLK_PERIS 0x0900
1774 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1775 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1776 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1777 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1778 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1779 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1780 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1781 #define ENABLE_SCLK_PERIS 0x0a00
1782 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1783 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1784 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1785 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1786 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1787 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1788 #define ENABLE_IP_PERIS0 0x0b00
1789 #define ENABLE_IP_PERIS1 0x0b04
1790 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1791 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1792 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1793 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1794 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1795 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1796 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1829 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1831 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1833 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1837 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1839 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1841 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1843 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1845 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1847 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1849 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1851 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1853 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1855 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1859 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1861 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1863 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1865 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1867 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1869 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1871 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1873 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1875 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1877 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1879 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1881 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1883 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1887 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1891 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1895 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1900 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1905 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1910 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1914 ENABLE_SCLK_PERIS, 10, 0, 0),
1916 ENABLE_SCLK_PERIS, 4, 0, 0),
1918 ENABLE_SCLK_PERIS, 3, 0, 0),
1922 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1926 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1930 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1934 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1938 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1942 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1964 #define MUX_SEL_FSYS0 0x0200
1965 #define MUX_SEL_FSYS1 0x0204
1966 #define MUX_SEL_FSYS2 0x0208
1967 #define MUX_SEL_FSYS3 0x020c
1968 #define MUX_SEL_FSYS4 0x0210
1969 #define MUX_ENABLE_FSYS0 0x0300
1970 #define MUX_ENABLE_FSYS1 0x0304
1971 #define MUX_ENABLE_FSYS2 0x0308
1972 #define MUX_ENABLE_FSYS3 0x030c
1973 #define MUX_ENABLE_FSYS4 0x0310
1974 #define MUX_STAT_FSYS0 0x0400
1975 #define MUX_STAT_FSYS1 0x0404
1976 #define MUX_STAT_FSYS2 0x0408
1977 #define MUX_STAT_FSYS3 0x040c
1978 #define MUX_STAT_FSYS4 0x0410
1979 #define MUX_IGNORE_FSYS2 0x0508
1980 #define MUX_IGNORE_FSYS3 0x050c
1981 #define ENABLE_ACLK_FSYS0 0x0800
1982 #define ENABLE_ACLK_FSYS1 0x0804
1983 #define ENABLE_PCLK_FSYS 0x0900
1984 #define ENABLE_SCLK_FSYS 0x0a00
1985 #define ENABLE_IP_FSYS0 0x0b00
1986 #define ENABLE_IP_FSYS1 0x0b04
2051 { MUX_SEL_FSYS0, 0 },
2052 { MUX_SEL_FSYS1, 0 },
2053 { MUX_SEL_FSYS2, 0 },
2054 { MUX_SEL_FSYS3, 0 },
2055 { MUX_SEL_FSYS4, 0 },
2062 0, 60000000),
2065 0, 125000000),
2069 0, 60000000),
2072 0, 125000000),
2075 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2077 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2080 0, 48000000),
2082 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2086 NULL, 0, 300000000),
2088 NULL, 0, 300000000),
2090 NULL, 0, 300000000),
2092 NULL, 0, 300000000),
2095 NULL, 0, 26000000),
2103 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2119 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2153 MUX_SEL_FSYS2, 0, 1),
2175 MUX_SEL_FSYS3, 0, 1),
2179 MUX_SEL_FSYS4, 0, 1),
2185 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2187 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2189 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2191 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2193 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2195 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2197 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2199 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2201 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2203 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2205 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2209 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2212 26, CLK_IGNORE_UNUSED, 0),
2214 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2216 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2219 22, CLK_IGNORE_UNUSED, 0),
2221 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2223 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2226 13, 0, 0),
2229 12, 0, 0),
2232 11, CLK_IGNORE_UNUSED, 0),
2235 10, CLK_IGNORE_UNUSED, 0),
2238 9, CLK_IGNORE_UNUSED, 0),
2241 8, CLK_IGNORE_UNUSED, 0),
2244 7, CLK_IGNORE_UNUSED, 0),
2247 6, CLK_IGNORE_UNUSED, 0),
2249 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2251 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2253 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2255 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2257 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2259 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2263 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2265 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2267 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2269 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2271 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2273 ENABLE_PCLK_FSYS, 5, 0, 0),
2275 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2277 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2279 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2281 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2284 0, CLK_IGNORE_UNUSED, 0),
2288 ENABLE_SCLK_FSYS, 21, 0, 0),
2292 ENABLE_SCLK_FSYS, 18, 0, 0),
2296 ENABLE_SCLK_FSYS, 17, 0, 0),
2299 16, 0, 0),
2302 15, 0, 0),
2305 14, 0, 0),
2308 13, 0, 0),
2311 12, 0, 0),
2315 ENABLE_SCLK_FSYS, 11, 0, 0),
2319 ENABLE_SCLK_FSYS, 10, 0, 0),
2323 ENABLE_SCLK_FSYS, 9, 0, 0),
2327 ENABLE_SCLK_FSYS, 8, 0, 0),
2331 ENABLE_SCLK_FSYS, 7, 0, 0),
2333 ENABLE_SCLK_FSYS, 6, 0, 0),
2335 ENABLE_SCLK_FSYS, 5, 0, 0),
2337 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2339 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2341 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2343 ENABLE_SCLK_FSYS, 1, 0, 0),
2345 ENABLE_SCLK_FSYS, 0, 0, 0),
2348 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2349 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2350 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2371 #define MUX_SEL_G2D0 0x0200
2372 #define MUX_SEL_ENABLE_G2D0 0x0300
2373 #define MUX_SEL_STAT_G2D0 0x0400
2374 #define DIV_G2D 0x0600
2375 #define DIV_STAT_G2D 0x0700
2376 #define DIV_ENABLE_ACLK_G2D 0x0800
2377 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2378 #define DIV_ENABLE_PCLK_G2D 0x0900
2379 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2380 #define DIV_ENABLE_IP_G2D0 0x0b00
2381 #define DIV_ENABLE_IP_G2D1 0x0b04
2382 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2398 { MUX_SEL_G2D0, 0 },
2410 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2416 DIV_G2D, 0, 2),
2422 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2424 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2426 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2428 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2430 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2433 7, 0, 0),
2435 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2437 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2439 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2441 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2443 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2445 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2447 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2451 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2455 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2457 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2459 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2461 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2463 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2465 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2467 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2469 0, 0, 0),
2473 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2494 #define DISP_PLL_LOCK 0x0000
2495 #define DISP_PLL_CON0 0x0100
2496 #define DISP_PLL_CON1 0x0104
2497 #define DISP_PLL_FREQ_DET 0x0108
2498 #define MUX_SEL_DISP0 0x0200
2499 #define MUX_SEL_DISP1 0x0204
2500 #define MUX_SEL_DISP2 0x0208
2501 #define MUX_SEL_DISP3 0x020c
2502 #define MUX_SEL_DISP4 0x0210
2503 #define MUX_ENABLE_DISP0 0x0300
2504 #define MUX_ENABLE_DISP1 0x0304
2505 #define MUX_ENABLE_DISP2 0x0308
2506 #define MUX_ENABLE_DISP3 0x030c
2507 #define MUX_ENABLE_DISP4 0x0310
2508 #define MUX_STAT_DISP0 0x0400
2509 #define MUX_STAT_DISP1 0x0404
2510 #define MUX_STAT_DISP2 0x0408
2511 #define MUX_STAT_DISP3 0x040c
2512 #define MUX_STAT_DISP4 0x0410
2513 #define MUX_IGNORE_DISP2 0x0508
2514 #define DIV_DISP 0x0600
2515 #define DIV_DISP_PLL_FREQ_DET 0x0604
2516 #define DIV_STAT_DISP 0x0700
2517 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2518 #define ENABLE_ACLK_DISP0 0x0800
2519 #define ENABLE_ACLK_DISP1 0x0804
2520 #define ENABLE_PCLK_DISP 0x0900
2521 #define ENABLE_SCLK_DISP 0x0a00
2522 #define ENABLE_IP_DISP0 0x0b00
2523 #define ENABLE_IP_DISP1 0x0b04
2524 #define CLKOUT_CMU_DISP 0x0c00
2525 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2557 { DISP_PLL_CON0, 0x85f40502 },
2559 { MUX_IGNORE_DISP2, 0x00111111 },
2560 { MUX_SEL_DISP0, 0 },
2561 { MUX_SEL_DISP1, 0 },
2562 { MUX_SEL_DISP2, 0 },
2563 { MUX_SEL_DISP3, 0 },
2564 { MUX_SEL_DISP4, 0 },
2624 1, 2, 0),
2626 1, 2, 0),
2631 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2632 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2635 NULL, 0, 188000000),
2637 NULL, 0, 100000000),
2640 NULL, 0, 300000000),
2642 NULL, 0, 166000000),
2648 0, 1),
2666 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2692 0, 1),
2702 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2717 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2735 DIV_DISP, 0, 2),
2741 ENABLE_ACLK_DISP0, 2, 0, 0),
2743 ENABLE_ACLK_DISP0, 0, 0, 0),
2747 ENABLE_ACLK_DISP1, 25, 0, 0),
2749 ENABLE_ACLK_DISP1, 24, 0, 0),
2751 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2753 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2755 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2757 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2759 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2761 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2763 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2765 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2767 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2769 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2771 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2774 12, CLK_IGNORE_UNUSED, 0),
2777 11, CLK_IGNORE_UNUSED, 0),
2780 10, CLK_IGNORE_UNUSED, 0),
2782 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2784 ENABLE_ACLK_DISP1, 7, 0, 0),
2786 ENABLE_ACLK_DISP1, 6, 0, 0),
2788 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2790 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2792 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2794 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2797 CLK_IGNORE_UNUSED, 0),
2800 0, CLK_IGNORE_UNUSED, 0),
2804 ENABLE_PCLK_DISP, 23, 0, 0),
2806 ENABLE_PCLK_DISP, 22, 0, 0),
2808 ENABLE_PCLK_DISP, 21, 0, 0),
2810 ENABLE_PCLK_DISP, 20, 0, 0),
2812 ENABLE_PCLK_DISP, 19, 0, 0),
2814 ENABLE_PCLK_DISP, 18, 0, 0),
2816 ENABLE_PCLK_DISP, 17, 0, 0),
2818 ENABLE_PCLK_DISP, 16, 0, 0),
2820 ENABLE_PCLK_DISP, 15, 0, 0),
2822 ENABLE_PCLK_DISP, 14, 0, 0),
2824 ENABLE_PCLK_DISP, 13, 0, 0),
2826 ENABLE_PCLK_DISP, 12, 0, 0),
2828 ENABLE_PCLK_DISP, 11, 0, 0),
2830 ENABLE_PCLK_DISP, 10, 0, 0),
2832 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2834 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2836 ENABLE_PCLK_DISP, 7, 0, 0),
2838 ENABLE_PCLK_DISP, 6, 0, 0),
2840 ENABLE_PCLK_DISP, 5, 0, 0),
2842 ENABLE_PCLK_DISP, 3, 0, 0),
2844 ENABLE_PCLK_DISP, 2, 0, 0),
2846 ENABLE_PCLK_DISP, 1, 0, 0),
2848 ENABLE_PCLK_DISP, 0, 0, 0),
2853 ENABLE_SCLK_DISP, 26, 0, 0),
2856 ENABLE_SCLK_DISP, 25, 0, 0),
2858 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2860 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2862 ENABLE_SCLK_DISP, 22, 0, 0),
2865 ENABLE_SCLK_DISP, 21, 0, 0),
2868 ENABLE_SCLK_DISP, 15, 0, 0),
2871 ENABLE_SCLK_DISP, 14, 0, 0),
2874 ENABLE_SCLK_DISP, 13, 0, 0),
2876 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2878 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2880 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2882 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2884 ENABLE_SCLK_DISP, 7, 0, 0),
2886 ENABLE_SCLK_DISP, 6, 0, 0),
2888 ENABLE_SCLK_DISP, 5, 0, 0),
2891 ENABLE_SCLK_DISP, 4, 0, 0),
2893 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2895 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2922 #define MUX_SEL_AUD0 0x0200
2923 #define MUX_SEL_AUD1 0x0204
2924 #define MUX_ENABLE_AUD0 0x0300
2925 #define MUX_ENABLE_AUD1 0x0304
2926 #define MUX_STAT_AUD0 0x0400
2927 #define DIV_AUD0 0x0600
2928 #define DIV_AUD1 0x0604
2929 #define DIV_STAT_AUD0 0x0700
2930 #define DIV_STAT_AUD1 0x0704
2931 #define ENABLE_ACLK_AUD 0x0800
2932 #define ENABLE_PCLK_AUD 0x0900
2933 #define ENABLE_SCLK_AUD0 0x0a00
2934 #define ENABLE_SCLK_AUD1 0x0a04
2935 #define ENABLE_IP_AUD0 0x0b00
2936 #define ENABLE_IP_AUD1 0x0b04
2954 { MUX_SEL_AUD0, 0 },
2955 { MUX_SEL_AUD1, 0 },
2963 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2964 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2965 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2971 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2977 MUX_SEL_AUD1, 0, 1),
2989 0, 4),
2999 DIV_AUD1, 0, 4),
3005 ENABLE_ACLK_AUD, 12, 0, 0),
3007 ENABLE_ACLK_AUD, 7, 0, 0),
3009 ENABLE_ACLK_AUD, 0, 4, 0),
3011 ENABLE_ACLK_AUD, 0, 3, 0),
3013 ENABLE_ACLK_AUD, 0, 2, 0),
3015 0, 1, 0),
3017 0, CLK_IGNORE_UNUSED, 0),
3021 13, 0, 0),
3023 12, 0, 0),
3025 11, 0, 0),
3027 ENABLE_PCLK_AUD, 10, 0, 0),
3029 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3031 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3033 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3035 ENABLE_PCLK_AUD, 6, 0, 0),
3037 ENABLE_PCLK_AUD, 5, 0, 0),
3039 ENABLE_PCLK_AUD, 4, 0, 0),
3041 ENABLE_PCLK_AUD, 3, 0, 0),
3043 2, 0, 0),
3045 ENABLE_PCLK_AUD, 0, 0, 0),
3049 2, CLK_IGNORE_UNUSED, 0),
3051 ENABLE_SCLK_AUD0, 1, 0, 0),
3053 0, 0, 0),
3057 ENABLE_SCLK_AUD1, 6, 0, 0),
3059 ENABLE_SCLK_AUD1, 5, 0, 0),
3061 ENABLE_SCLK_AUD1, 4, 0, 0),
3063 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3065 ENABLE_SCLK_AUD1, 2, 0, 0),
3067 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3069 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3090 * Register offset definitions for CMU_BUS{0|1|2}
3092 #define DIV_BUS 0x0600
3093 #define DIV_STAT_BUS 0x0700
3094 #define ENABLE_ACLK_BUS 0x0800
3095 #define ENABLE_PCLK_BUS 0x0900
3096 #define ENABLE_IP_BUS0 0x0b00
3097 #define ENABLE_IP_BUS1 0x0b04
3099 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3100 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3101 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3126 DIV_BUS, 0, 3),
3133 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3135 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3137 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3141 ENABLE_PCLK_BUS, 2, 0, 0),
3143 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3145 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3152 DIV_BUS, 0, 3),
3158 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3160 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3162 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3166 ENABLE_PCLK_BUS, 2, 0, 0),
3168 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3170 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3177 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3183 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3189 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3191 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3194 1, CLK_IGNORE_UNUSED, 0),
3197 0, CLK_IGNORE_UNUSED, 0),
3201 ENABLE_PCLK_BUS, 2, 0, 0),
3203 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3205 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3216 CMU_BUS_INFO_CLKS(0),
3244 exynos5433_cmu_bus_init(0);
3251 #define G3D_PLL_LOCK 0x0000
3252 #define G3D_PLL_CON0 0x0100
3253 #define G3D_PLL_CON1 0x0104
3254 #define G3D_PLL_FREQ_DET 0x010c
3255 #define MUX_SEL_G3D 0x0200
3256 #define MUX_ENABLE_G3D 0x0300
3257 #define MUX_STAT_G3D 0x0400
3258 #define DIV_G3D 0x0600
3259 #define DIV_G3D_PLL_FREQ_DET 0x0604
3260 #define DIV_STAT_G3D 0x0700
3261 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3262 #define ENABLE_ACLK_G3D 0x0800
3263 #define ENABLE_PCLK_G3D 0x0900
3264 #define ENABLE_SCLK_G3D 0x0a00
3265 #define ENABLE_IP_G3D0 0x0b00
3266 #define ENABLE_IP_G3D1 0x0b04
3267 #define CLKOUT_CMU_G3D 0x0c00
3268 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3269 #define CLK_STOPCTRL 0x1000
3291 { MUX_SEL_G3D, 0 },
3306 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3308 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3318 0, 3, CLK_SET_RATE_PARENT, 0),
3324 ENABLE_ACLK_G3D, 7, 0, 0),
3326 ENABLE_ACLK_G3D, 6, 0, 0),
3328 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3330 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3332 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3334 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3336 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3338 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3342 ENABLE_PCLK_G3D, 3, 0, 0),
3344 ENABLE_PCLK_G3D, 2, 0, 0),
3346 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3348 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3352 ENABLE_SCLK_G3D, 0, 0, 0),
3375 #define MUX_SEL_GSCL 0x0200
3376 #define MUX_ENABLE_GSCL 0x0300
3377 #define MUX_STAT_GSCL 0x0400
3378 #define ENABLE_ACLK_GSCL 0x0800
3379 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3380 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3381 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3382 #define ENABLE_PCLK_GSCL 0x0900
3383 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3384 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3385 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3386 #define ENABLE_IP_GSCL0 0x0b00
3387 #define ENABLE_IP_GSCL1 0x0b04
3388 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3389 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3390 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3411 { MUX_SEL_GSCL, 0 },
3412 { ENABLE_ACLK_GSCL, 0xfff },
3413 { ENABLE_PCLK_GSCL, 0xff },
3425 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3431 ENABLE_ACLK_GSCL, 11, 0, 0),
3433 ENABLE_ACLK_GSCL, 10, 0, 0),
3435 ENABLE_ACLK_GSCL, 9, 0, 0),
3438 8, CLK_IGNORE_UNUSED, 0),
3440 ENABLE_ACLK_GSCL, 7, 0, 0),
3442 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3445 CLK_IGNORE_UNUSED, 0),
3448 CLK_IGNORE_UNUSED, 0),
3450 ENABLE_ACLK_GSCL, 3, 0, 0),
3452 ENABLE_ACLK_GSCL, 2, 0, 0),
3454 ENABLE_ACLK_GSCL, 1, 0, 0),
3456 ENABLE_ACLK_GSCL, 0, 0, 0),
3460 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3464 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3468 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3472 ENABLE_PCLK_GSCL, 7, 0, 0),
3474 ENABLE_PCLK_GSCL, 6, 0, 0),
3476 ENABLE_PCLK_GSCL, 5, 0, 0),
3478 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3481 3, CLK_IGNORE_UNUSED, 0),
3483 ENABLE_PCLK_GSCL, 2, 0, 0),
3485 ENABLE_PCLK_GSCL, 1, 0, 0),
3487 ENABLE_PCLK_GSCL, 0, 0, 0),
3491 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3495 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3499 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3518 #define APOLLO_PLL_LOCK 0x0000
3519 #define APOLLO_PLL_CON0 0x0100
3520 #define APOLLO_PLL_CON1 0x0104
3521 #define APOLLO_PLL_FREQ_DET 0x010c
3522 #define MUX_SEL_APOLLO0 0x0200
3523 #define MUX_SEL_APOLLO1 0x0204
3524 #define MUX_SEL_APOLLO2 0x0208
3525 #define MUX_ENABLE_APOLLO0 0x0300
3526 #define MUX_ENABLE_APOLLO1 0x0304
3527 #define MUX_ENABLE_APOLLO2 0x0308
3528 #define MUX_STAT_APOLLO0 0x0400
3529 #define MUX_STAT_APOLLO1 0x0404
3530 #define MUX_STAT_APOLLO2 0x0408
3531 #define DIV_APOLLO0 0x0600
3532 #define DIV_APOLLO1 0x0604
3533 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3534 #define DIV_STAT_APOLLO0 0x0700
3535 #define DIV_STAT_APOLLO1 0x0704
3536 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3537 #define ENABLE_ACLK_APOLLO 0x0800
3538 #define ENABLE_PCLK_APOLLO 0x0900
3539 #define ENABLE_SCLK_APOLLO 0x0a00
3540 #define ENABLE_IP_APOLLO0 0x0b00
3541 #define ENABLE_IP_APOLLO1 0x0b04
3542 #define CLKOUT_CMU_APOLLO 0x0c00
3543 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3544 #define ARMCLK_STOPCTRL 0x1000
3545 #define APOLLO_PWR_CTRL 0x1020
3546 #define APOLLO_PWR_CTRL2 0x1024
3547 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3548 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3549 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3594 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3595 CLK_RECALC_NEW_RATES, 0),
3599 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3603 0, 1, CLK_SET_RATE_PARENT, 0),
3624 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3626 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3633 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3641 6, CLK_IGNORE_UNUSED, 0),
3644 5, CLK_IGNORE_UNUSED, 0),
3647 4, CLK_IGNORE_UNUSED, 0),
3650 3, CLK_IGNORE_UNUSED, 0),
3653 2, CLK_IGNORE_UNUSED, 0),
3656 1, CLK_IGNORE_UNUSED, 0),
3659 0, CLK_IGNORE_UNUSED, 0),
3664 2, CLK_IGNORE_UNUSED, 0),
3666 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3669 0, CLK_IGNORE_UNUSED, 0),
3673 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3675 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3683 (((hpm) << 4) | ((copy) << 0))
3696 { 0 },
3701 CLK_MOUT_BUS_PLL_APOLLO_USER, 0, 0x0,
3731 #define ATLAS_PLL_LOCK 0x0000
3732 #define ATLAS_PLL_CON0 0x0100
3733 #define ATLAS_PLL_CON1 0x0104
3734 #define ATLAS_PLL_FREQ_DET 0x010c
3735 #define MUX_SEL_ATLAS0 0x0200
3736 #define MUX_SEL_ATLAS1 0x0204
3737 #define MUX_SEL_ATLAS2 0x0208
3738 #define MUX_ENABLE_ATLAS0 0x0300
3739 #define MUX_ENABLE_ATLAS1 0x0304
3740 #define MUX_ENABLE_ATLAS2 0x0308
3741 #define MUX_STAT_ATLAS0 0x0400
3742 #define MUX_STAT_ATLAS1 0x0404
3743 #define MUX_STAT_ATLAS2 0x0408
3744 #define DIV_ATLAS0 0x0600
3745 #define DIV_ATLAS1 0x0604
3746 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3747 #define DIV_STAT_ATLAS0 0x0700
3748 #define DIV_STAT_ATLAS1 0x0704
3749 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3750 #define ENABLE_ACLK_ATLAS 0x0800
3751 #define ENABLE_PCLK_ATLAS 0x0900
3752 #define ENABLE_SCLK_ATLAS 0x0a00
3753 #define ENABLE_IP_ATLAS0 0x0b00
3754 #define ENABLE_IP_ATLAS1 0x0b04
3755 #define CLKOUT_CMU_ATLAS 0x0c00
3756 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3757 #define ARMCLK_STOPCTRL 0x1000
3758 #define ATLAS_PWR_CTRL 0x1020
3759 #define ATLAS_PWR_CTRL2 0x1024
3760 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3761 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3762 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3807 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3808 CLK_RECALC_NEW_RATES, 0),
3812 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3816 0, 1, CLK_SET_RATE_PARENT, 0),
3837 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3839 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3846 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3854 9, CLK_IGNORE_UNUSED, 0),
3857 8, CLK_IGNORE_UNUSED, 0),
3860 7, CLK_IGNORE_UNUSED, 0),
3863 6, CLK_IGNORE_UNUSED, 0),
3866 5, CLK_IGNORE_UNUSED, 0),
3869 4, CLK_IGNORE_UNUSED, 0),
3872 3, CLK_IGNORE_UNUSED, 0),
3875 2, CLK_IGNORE_UNUSED, 0),
3877 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3879 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3884 5, CLK_IGNORE_UNUSED, 0),
3887 4, CLK_IGNORE_UNUSED, 0),
3890 3, CLK_IGNORE_UNUSED, 0),
3892 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3894 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3896 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3900 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3902 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3904 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3906 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3908 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3910 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3912 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3914 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3922 (((hpm) << 4) | ((copy) << 0))
3940 { 0 },
3945 CLK_MOUT_BUS_PLL_ATLAS_USER, 0, 0x0,
3975 #define MUX_SEL_MSCL0 0x0200
3976 #define MUX_SEL_MSCL1 0x0204
3977 #define MUX_ENABLE_MSCL0 0x0300
3978 #define MUX_ENABLE_MSCL1 0x0304
3979 #define MUX_STAT_MSCL0 0x0400
3980 #define MUX_STAT_MSCL1 0x0404
3981 #define DIV_MSCL 0x0600
3982 #define DIV_STAT_MSCL 0x0700
3983 #define ENABLE_ACLK_MSCL 0x0800
3984 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3985 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3986 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3987 #define ENABLE_PCLK_MSCL 0x0900
3988 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3989 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3990 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3991 #define ENABLE_SCLK_MSCL 0x0a00
3992 #define ENABLE_IP_MSCL0 0x0b00
3993 #define ENABLE_IP_MSCL1 0x0b04
3994 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3995 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3996 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
4021 { MUX_SEL_MSCL0, 0 },
4022 { MUX_SEL_MSCL1, 0 },
4036 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4040 MUX_SEL_MSCL1, 0, 1),
4046 DIV_MSCL, 0, 3),
4052 ENABLE_ACLK_MSCL, 9, 0, 0),
4054 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4056 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4058 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4060 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4062 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4064 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4066 ENABLE_ACLK_MSCL, 2, 0, 0),
4068 ENABLE_ACLK_MSCL, 1, 0, 0),
4070 ENABLE_ACLK_MSCL, 0, 0, 0),
4076 0, CLK_IGNORE_UNUSED, 0),
4082 0, CLK_IGNORE_UNUSED, 0),
4087 0, CLK_IGNORE_UNUSED, 0),
4091 ENABLE_PCLK_MSCL, 7, 0, 0),
4093 ENABLE_PCLK_MSCL, 6, 0, 0),
4095 ENABLE_PCLK_MSCL, 5, 0, 0),
4097 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4099 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4101 ENABLE_PCLK_MSCL, 2, 0, 0),
4103 ENABLE_PCLK_MSCL, 1, 0, 0),
4105 ENABLE_PCLK_MSCL, 0, 0, 0),
4110 0, CLK_IGNORE_UNUSED, 0),
4115 0, CLK_IGNORE_UNUSED, 0),
4120 0, CLK_IGNORE_UNUSED, 0),
4123 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4124 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4145 #define MUX_SEL_MFC 0x0200
4146 #define MUX_ENABLE_MFC 0x0300
4147 #define MUX_STAT_MFC 0x0400
4148 #define DIV_MFC 0x0600
4149 #define DIV_STAT_MFC 0x0700
4150 #define ENABLE_ACLK_MFC 0x0800
4151 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4152 #define ENABLE_PCLK_MFC 0x0900
4153 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4154 #define ENABLE_IP_MFC0 0x0b00
4155 #define ENABLE_IP_MFC1 0x0b04
4156 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4172 { MUX_SEL_MFC, 0 },
4180 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4186 DIV_MFC, 0, 2),
4192 ENABLE_ACLK_MFC, 6, 0, 0),
4194 ENABLE_ACLK_MFC, 5, 0, 0),
4196 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4198 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4200 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4202 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4204 ENABLE_ACLK_MFC, 0, 0, 0),
4209 1, CLK_IGNORE_UNUSED, 0),
4212 0, CLK_IGNORE_UNUSED, 0),
4216 ENABLE_PCLK_MFC, 4, 0, 0),
4218 ENABLE_PCLK_MFC, 3, 0, 0),
4220 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4222 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4224 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4229 1, CLK_IGNORE_UNUSED, 0),
4232 0, CLK_IGNORE_UNUSED, 0),
4253 #define MUX_SEL_HEVC 0x0200
4254 #define MUX_ENABLE_HEVC 0x0300
4255 #define MUX_STAT_HEVC 0x0400
4256 #define DIV_HEVC 0x0600
4257 #define DIV_STAT_HEVC 0x0700
4258 #define ENABLE_ACLK_HEVC 0x0800
4259 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4260 #define ENABLE_PCLK_HEVC 0x0900
4261 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4262 #define ENABLE_IP_HEVC0 0x0b00
4263 #define ENABLE_IP_HEVC1 0x0b04
4264 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4280 { MUX_SEL_HEVC, 0 },
4288 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4294 DIV_HEVC, 0, 2),
4300 ENABLE_ACLK_HEVC, 6, 0, 0),
4302 ENABLE_ACLK_HEVC, 5, 0, 0),
4304 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4306 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4308 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4310 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4312 ENABLE_ACLK_HEVC, 0, 0, 0),
4318 1, CLK_IGNORE_UNUSED, 0),
4322 0, CLK_IGNORE_UNUSED, 0),
4326 ENABLE_PCLK_HEVC, 4, 0, 0),
4328 ENABLE_PCLK_HEVC, 3, 0, 0),
4330 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4332 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4334 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4339 1, CLK_IGNORE_UNUSED, 0),
4342 0, CLK_IGNORE_UNUSED, 0),
4363 #define MUX_SEL_ISP 0x0200
4364 #define MUX_ENABLE_ISP 0x0300
4365 #define MUX_STAT_ISP 0x0400
4366 #define DIV_ISP 0x0600
4367 #define DIV_STAT_ISP 0x0700
4368 #define ENABLE_ACLK_ISP0 0x0800
4369 #define ENABLE_ACLK_ISP1 0x0804
4370 #define ENABLE_ACLK_ISP2 0x0808
4371 #define ENABLE_PCLK_ISP 0x0900
4372 #define ENABLE_SCLK_ISP 0x0a00
4373 #define ENABLE_IP_ISP0 0x0b00
4374 #define ENABLE_IP_ISP1 0x0b04
4375 #define ENABLE_IP_ISP2 0x0b08
4376 #define ENABLE_IP_ISP3 0x0b0c
4394 { MUX_SEL_ISP, 0 },
4403 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4405 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4417 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4423 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4425 ENABLE_ACLK_ISP0, 5, 0, 0),
4427 ENABLE_ACLK_ISP0, 4, 0, 0),
4429 ENABLE_ACLK_ISP0, 3, 0, 0),
4431 ENABLE_ACLK_ISP0, 2, 0, 0),
4433 ENABLE_ACLK_ISP0, 1, 0, 0),
4435 ENABLE_ACLK_ISP0, 0, 0, 0),
4440 17, CLK_IGNORE_UNUSED, 0),
4443 16, CLK_IGNORE_UNUSED, 0),
4446 15, CLK_IGNORE_UNUSED, 0),
4449 14, CLK_IGNORE_UNUSED, 0),
4452 13, CLK_IGNORE_UNUSED, 0),
4455 12, CLK_IGNORE_UNUSED, 0),
4458 11, CLK_IGNORE_UNUSED, 0),
4461 10, CLK_IGNORE_UNUSED, 0),
4464 9, CLK_IGNORE_UNUSED, 0),
4467 8, CLK_IGNORE_UNUSED, 0),
4470 7, CLK_IGNORE_UNUSED, 0),
4472 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4474 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4477 4, CLK_IGNORE_UNUSED, 0),
4480 3, CLK_IGNORE_UNUSED, 0),
4482 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4484 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4486 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4491 13, CLK_IGNORE_UNUSED, 0),
4493 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4495 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4497 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4500 9, CLK_IGNORE_UNUSED, 0),
4502 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4504 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4507 6, CLK_IGNORE_UNUSED, 0),
4509 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4511 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4513 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4516 2, CLK_IGNORE_UNUSED, 0),
4518 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4520 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4524 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4526 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4528 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4530 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4532 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4534 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4536 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4538 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4540 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4542 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4544 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4546 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4548 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4550 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4552 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4554 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4556 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4558 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4561 7, CLK_IGNORE_UNUSED, 0),
4563 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4565 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4567 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4569 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4571 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4573 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4575 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4580 5, CLK_IGNORE_UNUSED, 0),
4583 4, CLK_IGNORE_UNUSED, 0),
4586 3, CLK_IGNORE_UNUSED, 0),
4589 2, CLK_IGNORE_UNUSED, 0),
4592 1, CLK_IGNORE_UNUSED, 0),
4595 0, CLK_IGNORE_UNUSED, 0),
4616 #define MUX_SEL_CAM00 0x0200
4617 #define MUX_SEL_CAM01 0x0204
4618 #define MUX_SEL_CAM02 0x0208
4619 #define MUX_SEL_CAM03 0x020c
4620 #define MUX_SEL_CAM04 0x0210
4621 #define MUX_ENABLE_CAM00 0x0300
4622 #define MUX_ENABLE_CAM01 0x0304
4623 #define MUX_ENABLE_CAM02 0x0308
4624 #define MUX_ENABLE_CAM03 0x030c
4625 #define MUX_ENABLE_CAM04 0x0310
4626 #define MUX_STAT_CAM00 0x0400
4627 #define MUX_STAT_CAM01 0x0404
4628 #define MUX_STAT_CAM02 0x0408
4629 #define MUX_STAT_CAM03 0x040c
4630 #define MUX_STAT_CAM04 0x0410
4631 #define MUX_IGNORE_CAM01 0x0504
4632 #define DIV_CAM00 0x0600
4633 #define DIV_CAM01 0x0604
4634 #define DIV_CAM02 0x0608
4635 #define DIV_CAM03 0x060c
4636 #define DIV_STAT_CAM00 0x0700
4637 #define DIV_STAT_CAM01 0x0704
4638 #define DIV_STAT_CAM02 0x0708
4639 #define DIV_STAT_CAM03 0x070c
4640 #define ENABLE_ACLK_CAM00 0X0800
4641 #define ENABLE_ACLK_CAM01 0X0804
4642 #define ENABLE_ACLK_CAM02 0X0808
4643 #define ENABLE_PCLK_CAM0 0X0900
4644 #define ENABLE_SCLK_CAM0 0X0a00
4645 #define ENABLE_IP_CAM00 0X0b00
4646 #define ENABLE_IP_CAM01 0X0b04
4647 #define ENABLE_IP_CAM02 0X0b08
4648 #define ENABLE_IP_CAM03 0X0b0C
4678 { MUX_SEL_CAM00, 0 },
4679 { MUX_SEL_CAM01, 0 },
4680 { MUX_SEL_CAM02, 0 },
4681 { MUX_SEL_CAM03, 0 },
4682 { MUX_SEL_CAM04, 0 },
4745 NULL, 0, 100000000),
4747 NULL, 0, 100000000),
4757 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4767 MUX_SEL_CAM01, 0, 1),
4783 MUX_SEL_CAM02, 0, 1),
4801 MUX_SEL_CAM03, 0, 1),
4821 MUX_SEL_CAM04, 0, 1),
4831 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4845 DIV_CAM01, 0, 3),
4859 DIV_CAM02, 0, 3),
4868 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4874 6, 0, 0),
4876 5, 0, 0),
4878 4, 0, 0),
4880 3, 0, 0),
4882 ENABLE_ACLK_CAM00, 2, 0, 0),
4884 ENABLE_ACLK_CAM00, 1, 0, 0),
4886 ENABLE_ACLK_CAM00, 0, 0, 0),
4890 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4892 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4894 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4896 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4898 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4900 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4902 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4904 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4907 23, CLK_IGNORE_UNUSED, 0),
4910 22, CLK_IGNORE_UNUSED, 0),
4913 21, CLK_IGNORE_UNUSED, 0),
4916 20, CLK_IGNORE_UNUSED, 0),
4919 19, CLK_IGNORE_UNUSED, 0),
4922 18, CLK_IGNORE_UNUSED, 0),
4925 17, CLK_IGNORE_UNUSED, 0),
4928 16, CLK_IGNORE_UNUSED, 0),
4931 15, CLK_IGNORE_UNUSED, 0),
4934 14, CLK_IGNORE_UNUSED, 0),
4937 13, CLK_IGNORE_UNUSED, 0),
4940 12, CLK_IGNORE_UNUSED, 0),
4943 11, CLK_IGNORE_UNUSED, 0),
4946 10, CLK_IGNORE_UNUSED, 0),
4949 9, CLK_IGNORE_UNUSED, 0),
4952 8, CLK_IGNORE_UNUSED, 0),
4955 7, CLK_IGNORE_UNUSED, 0),
4958 6, CLK_IGNORE_UNUSED, 0),
4960 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4962 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4964 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4966 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4968 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4970 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4974 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4976 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4978 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4980 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4982 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4984 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4986 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4988 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4990 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4992 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4996 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4998 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
5000 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
5002 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
5004 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
5006 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
5008 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
5010 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
5012 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
5014 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
5016 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
5018 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
5020 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
5023 12, CLK_IGNORE_UNUSED, 0),
5026 11, CLK_IGNORE_UNUSED, 0),
5029 10, CLK_IGNORE_UNUSED, 0),
5031 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5033 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5036 7, CLK_IGNORE_UNUSED, 0),
5038 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5040 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5042 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5044 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5046 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5048 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5050 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5055 ENABLE_SCLK_CAM0, 8, 0, 0),
5058 ENABLE_SCLK_CAM0, 7, 0, 0),
5060 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5062 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5064 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5066 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5069 ENABLE_SCLK_CAM0, 2, 0, 0),
5072 ENABLE_SCLK_CAM0, 1, 0, 0),
5075 ENABLE_SCLK_CAM0, 0, 0, 0),
5098 #define MUX_SEL_CAM10 0x0200
5099 #define MUX_SEL_CAM11 0x0204
5100 #define MUX_SEL_CAM12 0x0208
5101 #define MUX_ENABLE_CAM10 0x0300
5102 #define MUX_ENABLE_CAM11 0x0304
5103 #define MUX_ENABLE_CAM12 0x0308
5104 #define MUX_STAT_CAM10 0x0400
5105 #define MUX_STAT_CAM11 0x0404
5106 #define MUX_STAT_CAM12 0x0408
5107 #define MUX_IGNORE_CAM11 0x0504
5108 #define DIV_CAM10 0x0600
5109 #define DIV_CAM11 0x0604
5110 #define DIV_STAT_CAM10 0x0700
5111 #define DIV_STAT_CAM11 0x0704
5112 #define ENABLE_ACLK_CAM10 0X0800
5113 #define ENABLE_ACLK_CAM11 0X0804
5114 #define ENABLE_ACLK_CAM12 0X0808
5115 #define ENABLE_PCLK_CAM1 0X0900
5116 #define ENABLE_SCLK_CAM1 0X0a00
5117 #define ENABLE_IP_CAM10 0X0b00
5118 #define ENABLE_IP_CAM11 0X0b04
5119 #define ENABLE_IP_CAM12 0X0b08
5142 { MUX_SEL_CAM10, 0 },
5143 { MUX_SEL_CAM11, 0 },
5144 { MUX_SEL_CAM12, 0 },
5175 0, 100000000),
5191 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5197 MUX_SEL_CAM11, 0, 1),
5211 MUX_SEL_CAM12, 0, 1),
5225 DIV_CAM10, 0, 3),
5235 DIV_CAM11, 0, 3),
5241 ENABLE_ACLK_CAM10, 4, 0, 0),
5243 ENABLE_ACLK_CAM10, 3, 0, 0),
5245 ENABLE_ACLK_CAM10, 1, 0, 0),
5247 ENABLE_ACLK_CAM10, 0, 0, 0),
5251 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5253 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5256 27, CLK_IGNORE_UNUSED, 0),
5259 26, CLK_IGNORE_UNUSED, 0),
5262 25, CLK_IGNORE_UNUSED, 0),
5265 24, CLK_IGNORE_UNUSED, 0),
5268 23, CLK_IGNORE_UNUSED, 0),
5271 22, CLK_IGNORE_UNUSED, 0),
5274 21, CLK_IGNORE_UNUSED, 0),
5277 20, CLK_IGNORE_UNUSED, 0),
5280 19, CLK_IGNORE_UNUSED, 0),
5283 18, CLK_IGNORE_UNUSED, 0),
5286 17, CLK_IGNORE_UNUSED, 0),
5289 16, CLK_IGNORE_UNUSED, 0),
5292 15, CLK_IGNORE_UNUSED, 0),
5294 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5297 13, CLK_IGNORE_UNUSED, 0),
5300 12, CLK_IGNORE_UNUSED, 0),
5302 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5304 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5307 9, CLK_IGNORE_UNUSED, 0),
5309 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5311 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5313 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5315 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5317 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5319 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5321 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5323 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5325 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5330 10, CLK_IGNORE_UNUSED, 0),
5332 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5335 8, CLK_IGNORE_UNUSED, 0),
5337 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5339 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5341 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5344 4, CLK_IGNORE_UNUSED, 0),
5347 3, CLK_IGNORE_UNUSED, 0),
5350 2, CLK_IGNORE_UNUSED, 0),
5352 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5355 0, CLK_IGNORE_UNUSED, 0),
5359 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5361 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5363 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5365 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5367 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5369 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5371 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5374 20, CLK_IGNORE_UNUSED, 0),
5377 19, CLK_IGNORE_UNUSED, 0),
5379 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5382 17, CLK_IGNORE_UNUSED, 0),
5384 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5386 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5389 14, CLK_IGNORE_UNUSED, 0),
5391 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5393 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5395 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5397 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5399 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5401 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5403 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5405 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5407 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5409 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5411 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5413 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5415 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5417 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5421 15, 0, 0),
5423 14, 0, 0),
5425 13, 0, 0),
5427 12, 0, 0),
5430 ENABLE_SCLK_CAM1, 11, 0, 0),
5432 ENABLE_SCLK_CAM1, 10, 0, 0),
5434 ENABLE_SCLK_CAM1, 9, 0, 0),
5436 ENABLE_SCLK_CAM1, 7, 0, 0),
5438 ENABLE_SCLK_CAM1, 6, 0, 0),
5440 ENABLE_SCLK_CAM1, 5, 0, 0),
5442 ENABLE_SCLK_CAM1, 4, 0, 0),
5444 ENABLE_SCLK_CAM1, 3, 0, 0),
5446 ENABLE_SCLK_CAM1, 2, 0, 0),
5448 ENABLE_SCLK_CAM1, 1, 0, 0),
5450 ENABLE_SCLK_CAM1, 0, 0, 0),
5473 #define ENABLE_ACLK_IMEM_SLIMSSS 0x080c
5474 #define ENABLE_PCLK_IMEM_SLIMSSS 0x0908
5484 ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5488 ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),