Lines Matching +full:0 +full:x00111111
50 #define ISP_PLL_LOCK 0x0000
51 #define AUD_PLL_LOCK 0x0004
52 #define ISP_PLL_CON0 0x0100
53 #define ISP_PLL_CON1 0x0104
54 #define ISP_PLL_FREQ_DET 0x0108
55 #define AUD_PLL_CON0 0x0110
56 #define AUD_PLL_CON1 0x0114
57 #define AUD_PLL_CON2 0x0118
58 #define AUD_PLL_FREQ_DET 0x011c
59 #define MUX_SEL_TOP0 0x0200
60 #define MUX_SEL_TOP1 0x0204
61 #define MUX_SEL_TOP2 0x0208
62 #define MUX_SEL_TOP3 0x020c
63 #define MUX_SEL_TOP4 0x0210
64 #define MUX_SEL_TOP_MSCL 0x0220
65 #define MUX_SEL_TOP_CAM1 0x0224
66 #define MUX_SEL_TOP_DISP 0x0228
67 #define MUX_SEL_TOP_FSYS0 0x0230
68 #define MUX_SEL_TOP_FSYS1 0x0234
69 #define MUX_SEL_TOP_PERIC0 0x0238
70 #define MUX_SEL_TOP_PERIC1 0x023c
71 #define MUX_ENABLE_TOP0 0x0300
72 #define MUX_ENABLE_TOP1 0x0304
73 #define MUX_ENABLE_TOP2 0x0308
74 #define MUX_ENABLE_TOP3 0x030c
75 #define MUX_ENABLE_TOP4 0x0310
76 #define MUX_ENABLE_TOP_MSCL 0x0320
77 #define MUX_ENABLE_TOP_CAM1 0x0324
78 #define MUX_ENABLE_TOP_DISP 0x0328
79 #define MUX_ENABLE_TOP_FSYS0 0x0330
80 #define MUX_ENABLE_TOP_FSYS1 0x0334
81 #define MUX_ENABLE_TOP_PERIC0 0x0338
82 #define MUX_ENABLE_TOP_PERIC1 0x033c
83 #define MUX_STAT_TOP0 0x0400
84 #define MUX_STAT_TOP1 0x0404
85 #define MUX_STAT_TOP2 0x0408
86 #define MUX_STAT_TOP3 0x040c
87 #define MUX_STAT_TOP4 0x0410
88 #define MUX_STAT_TOP_MSCL 0x0420
89 #define MUX_STAT_TOP_CAM1 0x0424
90 #define MUX_STAT_TOP_FSYS0 0x0430
91 #define MUX_STAT_TOP_FSYS1 0x0434
92 #define MUX_STAT_TOP_PERIC0 0x0438
93 #define MUX_STAT_TOP_PERIC1 0x043c
94 #define DIV_TOP0 0x0600
95 #define DIV_TOP1 0x0604
96 #define DIV_TOP2 0x0608
97 #define DIV_TOP3 0x060c
98 #define DIV_TOP4 0x0610
99 #define DIV_TOP_MSCL 0x0618
100 #define DIV_TOP_CAM10 0x061c
101 #define DIV_TOP_CAM11 0x0620
102 #define DIV_TOP_FSYS0 0x062c
103 #define DIV_TOP_FSYS1 0x0630
104 #define DIV_TOP_FSYS2 0x0634
105 #define DIV_TOP_PERIC0 0x0638
106 #define DIV_TOP_PERIC1 0x063c
107 #define DIV_TOP_PERIC2 0x0640
108 #define DIV_TOP_PERIC3 0x0644
109 #define DIV_TOP_PERIC4 0x0648
110 #define DIV_TOP_PLL_FREQ_DET 0x064c
111 #define DIV_STAT_TOP0 0x0700
112 #define DIV_STAT_TOP1 0x0704
113 #define DIV_STAT_TOP2 0x0708
114 #define DIV_STAT_TOP3 0x070c
115 #define DIV_STAT_TOP4 0x0710
116 #define DIV_STAT_TOP_MSCL 0x0718
117 #define DIV_STAT_TOP_CAM10 0x071c
118 #define DIV_STAT_TOP_CAM11 0x0720
119 #define DIV_STAT_TOP_FSYS0 0x072c
120 #define DIV_STAT_TOP_FSYS1 0x0730
121 #define DIV_STAT_TOP_FSYS2 0x0734
122 #define DIV_STAT_TOP_PERIC0 0x0738
123 #define DIV_STAT_TOP_PERIC1 0x073c
124 #define DIV_STAT_TOP_PERIC2 0x0740
125 #define DIV_STAT_TOP_PERIC3 0x0744
126 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
127 #define ENABLE_ACLK_TOP 0x0800
128 #define ENABLE_SCLK_TOP 0x0a00
129 #define ENABLE_SCLK_TOP_MSCL 0x0a04
130 #define ENABLE_SCLK_TOP_CAM1 0x0a08
131 #define ENABLE_SCLK_TOP_DISP 0x0a0c
132 #define ENABLE_SCLK_TOP_FSYS 0x0a10
133 #define ENABLE_SCLK_TOP_PERIC 0x0a14
134 #define ENABLE_IP_TOP 0x0b00
135 #define ENABLE_CMU_TOP 0x0c00
136 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
203 { ENABLE_ACLK_TOP, 0x67ecffed },
205 { ENABLE_SCLK_TOP_PERIC, 0x38 },
207 { ISP_PLL_CON0, 0x85cc0502 },
209 { AUD_PLL_CON0, 0x84830202 },
260 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
264 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
265 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
266 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
268 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
269 /* XspiCLK[4:0] input clock for SPI */
270 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
271 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
272 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
273 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
274 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
276 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
284 0, 1),
294 MUX_SEL_TOP1, 0, 1),
308 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
322 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
330 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
338 MUX_SEL_TOP_MSCL, 0, 1),
352 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
370 MUX_SEL_TOP_FSYS0, 0, 1),
380 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
398 MUX_SEL_TOP_PERIC0, 0, 1),
408 MUX_SEL_TOP_PERIC1, 0, 2),
412 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
432 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
446 DIV_TOP1, 0, 3),
452 DIV_TOP2, 0, 3),
468 "mout_bus_pll_user", DIV_TOP3, 0, 3),
476 DIV_TOP4, 0, 3),
480 DIV_TOP_MSCL, 0, 4),
492 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
506 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
514 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
516 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
522 DIV_TOP_FSYS1, 0, 4),
532 DIV_TOP_FSYS2, 0, 4),
542 DIV_TOP_PERIC0, 0, 4),
548 DIV_TOP_PERIC1, 0, 4),
556 DIV_TOP_PERIC2, 0, 4),
566 DIV_TOP_PERIC3, 0, 4),
576 DIV_TOP_PERIC4, 0, 4),
582 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
585 29, CLK_IGNORE_UNUSED, 0),
588 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
591 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
594 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
597 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
600 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
603 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
606 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
609 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
612 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
615 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
618 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
621 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
624 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
627 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
630 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
633 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
636 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
639 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
642 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
645 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
648 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
650 ENABLE_ACLK_TOP, 0,
651 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
655 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
659 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
661 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
663 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
665 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
667 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
669 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
671 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
675 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
676 CLK_IGNORE_UNUSED, 0),
680 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
682 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
684 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
686 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
689 3, CLK_SET_RATE_PARENT, 0),
692 1, CLK_SET_RATE_PARENT, 0),
695 0, CLK_SET_RATE_PARENT, 0),
699 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
701 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
703 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
705 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
707 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
710 CLK_IGNORE_UNUSED, 0),
713 CLK_IGNORE_UNUSED, 0),
716 CLK_IGNORE_UNUSED, 0),
718 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
720 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
722 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
726 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
728 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
730 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
738 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
739 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
740 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
741 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
742 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
743 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
744 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
745 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
746 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
747 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
748 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
749 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
750 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
751 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
791 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
793 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
798 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
799 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
841 #define MPHY_PLL_LOCK 0x0000
842 #define MPHY_PLL_CON0 0x0100
843 #define MPHY_PLL_CON1 0x0104
844 #define MPHY_PLL_FREQ_DET 0x010c
845 #define MUX_SEL_CPIF0 0x0200
846 #define DIV_CPIF 0x0600
847 #define ENABLE_SCLK_CPIF 0x0a00
861 { ENABLE_SCLK_CPIF, 0x3ff },
863 { MPHY_PLL_CON0, 0x81c70601 },
877 0, 1),
883 0, 6),
889 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
891 ENABLE_SCLK_CPIF, 4, 0, 0),
920 #define MEM0_PLL_LOCK 0x0000
921 #define MEM1_PLL_LOCK 0x0004
922 #define BUS_PLL_LOCK 0x0008
923 #define MFC_PLL_LOCK 0x000c
924 #define MEM0_PLL_CON0 0x0100
925 #define MEM0_PLL_CON1 0x0104
926 #define MEM0_PLL_FREQ_DET 0x010c
927 #define MEM1_PLL_CON0 0x0110
928 #define MEM1_PLL_CON1 0x0114
929 #define MEM1_PLL_FREQ_DET 0x011c
930 #define BUS_PLL_CON0 0x0120
931 #define BUS_PLL_CON1 0x0124
932 #define BUS_PLL_FREQ_DET 0x012c
933 #define MFC_PLL_CON0 0x0130
934 #define MFC_PLL_CON1 0x0134
935 #define MFC_PLL_FREQ_DET 0x013c
936 #define MUX_SEL_MIF0 0x0200
937 #define MUX_SEL_MIF1 0x0204
938 #define MUX_SEL_MIF2 0x0208
939 #define MUX_SEL_MIF3 0x020c
940 #define MUX_SEL_MIF4 0x0210
941 #define MUX_SEL_MIF5 0x0214
942 #define MUX_SEL_MIF6 0x0218
943 #define MUX_SEL_MIF7 0x021c
944 #define MUX_ENABLE_MIF0 0x0300
945 #define MUX_ENABLE_MIF1 0x0304
946 #define MUX_ENABLE_MIF2 0x0308
947 #define MUX_ENABLE_MIF3 0x030c
948 #define MUX_ENABLE_MIF4 0x0310
949 #define MUX_ENABLE_MIF5 0x0314
950 #define MUX_ENABLE_MIF6 0x0318
951 #define MUX_ENABLE_MIF7 0x031c
952 #define MUX_STAT_MIF0 0x0400
953 #define MUX_STAT_MIF1 0x0404
954 #define MUX_STAT_MIF2 0x0408
955 #define MUX_STAT_MIF3 0x040c
956 #define MUX_STAT_MIF4 0x0410
957 #define MUX_STAT_MIF5 0x0414
958 #define MUX_STAT_MIF6 0x0418
959 #define MUX_STAT_MIF7 0x041c
960 #define DIV_MIF1 0x0604
961 #define DIV_MIF2 0x0608
962 #define DIV_MIF3 0x060c
963 #define DIV_MIF4 0x0610
964 #define DIV_MIF5 0x0614
965 #define DIV_MIF_PLL_FREQ_DET 0x0618
966 #define DIV_STAT_MIF1 0x0704
967 #define DIV_STAT_MIF2 0x0708
968 #define DIV_STAT_MIF3 0x070c
969 #define DIV_STAT_MIF4 0x0710
970 #define DIV_STAT_MIF5 0x0714
971 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
972 #define ENABLE_ACLK_MIF0 0x0800
973 #define ENABLE_ACLK_MIF1 0x0804
974 #define ENABLE_ACLK_MIF2 0x0808
975 #define ENABLE_ACLK_MIF3 0x080c
976 #define ENABLE_PCLK_MIF 0x0900
977 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
978 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
979 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
980 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
981 #define ENABLE_SCLK_MIF 0x0a00
982 #define ENABLE_IP_MIF0 0x0b00
983 #define ENABLE_IP_MIF1 0x0b04
984 #define ENABLE_IP_MIF2 0x0b08
985 #define ENABLE_IP_MIF3 0x0b0c
986 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
987 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
988 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
989 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
990 #define CLKOUT_CMU_MIF 0x0c00
991 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
992 #define DREX_FREQ_CTRL0 0x1000
993 #define DREX_FREQ_CTRL1 0x1004
994 #define PAUSE 0x1008
995 #define DDRPHY_LOCK_CTRL 0x100c
1125 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1126 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1127 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1128 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1148 0, 1),
1168 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1174 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1188 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1202 MUX_SEL_MIF5, 0, 1),
1210 MUX_SEL_MIF6, 0, 1),
1224 MUX_SEL_MIF7, 0, 1),
1250 DIV_MIF2, 0, 3),
1258 DIV_MIF3, 0, 3),
1274 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1278 0, 3),
1284 19, CLK_IGNORE_UNUSED, 0),
1286 18, CLK_IGNORE_UNUSED, 0),
1288 17, CLK_IGNORE_UNUSED, 0),
1290 16, CLK_IGNORE_UNUSED, 0),
1292 15, CLK_IGNORE_UNUSED, 0),
1294 14, CLK_IGNORE_UNUSED, 0),
1296 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1298 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1300 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1302 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1304 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1306 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1308 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1310 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1312 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1314 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1316 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1318 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1320 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1322 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1327 CLK_IGNORE_UNUSED, 0),
1330 27, CLK_IGNORE_UNUSED, 0),
1333 26, CLK_IGNORE_UNUSED, 0),
1336 25, CLK_IGNORE_UNUSED, 0),
1339 24, CLK_IGNORE_UNUSED, 0),
1342 23, CLK_IGNORE_UNUSED, 0),
1345 22, CLK_IGNORE_UNUSED, 0),
1348 21, CLK_IGNORE_UNUSED, 0),
1351 20, CLK_IGNORE_UNUSED, 0),
1354 19, CLK_IGNORE_UNUSED, 0),
1357 18, CLK_IGNORE_UNUSED, 0),
1360 17, CLK_IGNORE_UNUSED, 0),
1363 16, CLK_IGNORE_UNUSED, 0),
1366 15, CLK_IGNORE_UNUSED, 0),
1369 14, CLK_IGNORE_UNUSED, 0),
1372 13, CLK_IGNORE_UNUSED, 0),
1375 12, CLK_IGNORE_UNUSED, 0),
1378 11, CLK_IGNORE_UNUSED, 0),
1381 10, CLK_IGNORE_UNUSED, 0),
1383 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1385 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1387 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1389 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1391 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1393 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1395 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1397 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1399 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1401 0, CLK_IGNORE_UNUSED, 0),
1405 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1407 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1409 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1411 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1413 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1415 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1417 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1420 CLK_IGNORE_UNUSED, 0),
1423 5, CLK_IGNORE_UNUSED, 0),
1425 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1428 3, CLK_IGNORE_UNUSED, 0),
1430 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1435 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1438 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1440 ENABLE_ACLK_MIF3, 0,
1441 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1445 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1447 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1449 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1451 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1453 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1455 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1458 CLK_IGNORE_UNUSED, 0),
1460 ENABLE_PCLK_MIF, 19, 0, 0),
1462 ENABLE_PCLK_MIF, 18, 0, 0),
1464 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1466 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1468 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1470 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1472 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1474 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1476 ENABLE_PCLK_MIF, 11, 0, 0),
1478 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1480 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1482 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1484 ENABLE_PCLK_MIF, 7, 0, 0),
1486 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1488 ENABLE_PCLK_MIF, 5, 0, 0),
1490 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1492 ENABLE_PCLK_MIF, 2, 0, 0),
1494 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1498 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1499 CLK_IGNORE_UNUSED, 0),
1503 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1504 CLK_IGNORE_UNUSED, 0),
1508 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1512 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1516 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1519 14, CLK_IGNORE_UNUSED, 0),
1521 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1523 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1526 7, CLK_IGNORE_UNUSED, 0),
1529 6, CLK_IGNORE_UNUSED, 0),
1532 5, CLK_IGNORE_UNUSED, 0),
1535 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1537 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1539 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1541 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1543 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1572 #define DIV_PERIC 0x0600
1573 #define DIV_STAT_PERIC 0x0700
1574 #define ENABLE_ACLK_PERIC 0x0800
1575 #define ENABLE_PCLK_PERIC0 0x0900
1576 #define ENABLE_PCLK_PERIC1 0x0904
1577 #define ENABLE_SCLK_PERIC 0x0A00
1578 #define ENABLE_IP_PERIC0 0x0B00
1579 #define ENABLE_IP_PERIC1 0x0B04
1580 #define ENABLE_IP_PERIC2 0x0B08
1594 /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1595 { ENABLE_PCLK_PERIC0, 0xe00ff000 },
1596 /* sclk: uart2-0 */
1597 { ENABLE_SCLK_PERIC, 0x7 },
1603 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1609 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1611 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1613 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1615 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1619 31, CLK_SET_RATE_PARENT, 0),
1621 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1623 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1625 28, CLK_SET_RATE_PARENT, 0),
1627 26, CLK_SET_RATE_PARENT, 0),
1629 25, CLK_SET_RATE_PARENT, 0),
1631 24, CLK_SET_RATE_PARENT, 0),
1633 23, CLK_SET_RATE_PARENT, 0),
1635 22, CLK_SET_RATE_PARENT, 0),
1637 21, CLK_SET_RATE_PARENT, 0),
1639 20, CLK_SET_RATE_PARENT, 0),
1641 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1643 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1645 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1647 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1650 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1652 14, CLK_SET_RATE_PARENT, 0),
1654 13, CLK_SET_RATE_PARENT, 0),
1656 12, CLK_SET_RATE_PARENT, 0),
1658 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1660 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1662 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1664 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1666 7, CLK_SET_RATE_PARENT, 0),
1668 6, CLK_SET_RATE_PARENT, 0),
1670 5, CLK_SET_RATE_PARENT, 0),
1672 4, CLK_SET_RATE_PARENT, 0),
1674 3, CLK_SET_RATE_PARENT, 0),
1676 2, CLK_SET_RATE_PARENT, 0),
1678 1, CLK_SET_RATE_PARENT, 0),
1680 0, CLK_SET_RATE_PARENT, 0),
1684 9, CLK_SET_RATE_PARENT, 0),
1686 8, CLK_SET_RATE_PARENT, 0),
1688 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1690 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1692 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1694 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1696 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1698 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1700 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1702 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1706 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1708 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1710 19, CLK_SET_RATE_PARENT, 0),
1712 18, CLK_SET_RATE_PARENT, 0),
1714 17, 0, 0),
1716 16, 0, 0),
1717 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1719 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1721 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1723 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1726 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1728 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1730 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1733 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1735 5, CLK_SET_RATE_PARENT, 0),
1737 4, CLK_SET_RATE_PARENT, 0),
1739 3, CLK_SET_RATE_PARENT, 0),
1742 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1745 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1747 ENABLE_SCLK_PERIC, 0,
1748 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1774 #define ENABLE_ACLK_PERIS 0x0800
1775 #define ENABLE_PCLK_PERIS 0x0900
1776 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1777 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1778 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1779 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1780 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1781 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1782 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1783 #define ENABLE_SCLK_PERIS 0x0a00
1784 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1785 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1786 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1787 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1788 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1789 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1790 #define ENABLE_IP_PERIS0 0x0b00
1791 #define ENABLE_IP_PERIS1 0x0b04
1792 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1793 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1794 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1795 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1796 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1797 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1798 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1831 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1833 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1835 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1839 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1841 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1843 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1845 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1847 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1849 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1851 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1853 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1855 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1857 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1861 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1863 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1865 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1867 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1869 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1871 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1873 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1875 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1877 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1879 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1881 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1883 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1885 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1889 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1893 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1897 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1902 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1907 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1912 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1916 ENABLE_SCLK_PERIS, 10, 0, 0),
1918 ENABLE_SCLK_PERIS, 4, 0, 0),
1920 ENABLE_SCLK_PERIS, 3, 0, 0),
1924 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1928 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1932 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1936 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1940 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1944 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1966 #define MUX_SEL_FSYS0 0x0200
1967 #define MUX_SEL_FSYS1 0x0204
1968 #define MUX_SEL_FSYS2 0x0208
1969 #define MUX_SEL_FSYS3 0x020c
1970 #define MUX_SEL_FSYS4 0x0210
1971 #define MUX_ENABLE_FSYS0 0x0300
1972 #define MUX_ENABLE_FSYS1 0x0304
1973 #define MUX_ENABLE_FSYS2 0x0308
1974 #define MUX_ENABLE_FSYS3 0x030c
1975 #define MUX_ENABLE_FSYS4 0x0310
1976 #define MUX_STAT_FSYS0 0x0400
1977 #define MUX_STAT_FSYS1 0x0404
1978 #define MUX_STAT_FSYS2 0x0408
1979 #define MUX_STAT_FSYS3 0x040c
1980 #define MUX_STAT_FSYS4 0x0410
1981 #define MUX_IGNORE_FSYS2 0x0508
1982 #define MUX_IGNORE_FSYS3 0x050c
1983 #define ENABLE_ACLK_FSYS0 0x0800
1984 #define ENABLE_ACLK_FSYS1 0x0804
1985 #define ENABLE_PCLK_FSYS 0x0900
1986 #define ENABLE_SCLK_FSYS 0x0a00
1987 #define ENABLE_IP_FSYS0 0x0b00
1988 #define ENABLE_IP_FSYS1 0x0b04
2053 { MUX_SEL_FSYS0, 0 },
2054 { MUX_SEL_FSYS1, 0 },
2055 { MUX_SEL_FSYS2, 0 },
2056 { MUX_SEL_FSYS3, 0 },
2057 { MUX_SEL_FSYS4, 0 },
2064 0, 60000000),
2067 0, 125000000),
2071 0, 60000000),
2074 0, 125000000),
2077 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2079 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2082 0, 48000000),
2084 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2088 NULL, 0, 300000000),
2090 NULL, 0, 300000000),
2092 NULL, 0, 300000000),
2094 NULL, 0, 300000000),
2097 NULL, 0, 26000000),
2105 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2121 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2155 MUX_SEL_FSYS2, 0, 1),
2177 MUX_SEL_FSYS3, 0, 1),
2181 MUX_SEL_FSYS4, 0, 1),
2187 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2189 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2191 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2193 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2195 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2197 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2199 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2201 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2203 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2205 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2207 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2211 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2214 26, CLK_IGNORE_UNUSED, 0),
2216 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2218 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2221 22, CLK_IGNORE_UNUSED, 0),
2223 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2225 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2228 13, 0, 0),
2231 12, 0, 0),
2234 11, CLK_IGNORE_UNUSED, 0),
2237 10, CLK_IGNORE_UNUSED, 0),
2240 9, CLK_IGNORE_UNUSED, 0),
2243 8, CLK_IGNORE_UNUSED, 0),
2246 7, CLK_IGNORE_UNUSED, 0),
2249 6, CLK_IGNORE_UNUSED, 0),
2251 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2253 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2255 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2257 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2259 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2261 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2265 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2267 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2269 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2271 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2273 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2275 ENABLE_PCLK_FSYS, 5, 0, 0),
2277 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2279 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2281 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2283 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2286 0, CLK_IGNORE_UNUSED, 0),
2290 ENABLE_SCLK_FSYS, 21, 0, 0),
2294 ENABLE_SCLK_FSYS, 18, 0, 0),
2298 ENABLE_SCLK_FSYS, 17, 0, 0),
2301 16, 0, 0),
2304 15, 0, 0),
2307 14, 0, 0),
2310 13, 0, 0),
2313 12, 0, 0),
2317 ENABLE_SCLK_FSYS, 11, 0, 0),
2321 ENABLE_SCLK_FSYS, 10, 0, 0),
2325 ENABLE_SCLK_FSYS, 9, 0, 0),
2329 ENABLE_SCLK_FSYS, 8, 0, 0),
2333 ENABLE_SCLK_FSYS, 7, 0, 0),
2335 ENABLE_SCLK_FSYS, 6, 0, 0),
2337 ENABLE_SCLK_FSYS, 5, 0, 0),
2339 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2341 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2343 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2345 ENABLE_SCLK_FSYS, 1, 0, 0),
2347 ENABLE_SCLK_FSYS, 0, 0, 0),
2350 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2351 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2352 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2373 #define MUX_SEL_G2D0 0x0200
2374 #define MUX_SEL_ENABLE_G2D0 0x0300
2375 #define MUX_SEL_STAT_G2D0 0x0400
2376 #define DIV_G2D 0x0600
2377 #define DIV_STAT_G2D 0x0700
2378 #define DIV_ENABLE_ACLK_G2D 0x0800
2379 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2380 #define DIV_ENABLE_PCLK_G2D 0x0900
2381 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2382 #define DIV_ENABLE_IP_G2D0 0x0b00
2383 #define DIV_ENABLE_IP_G2D1 0x0b04
2384 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2400 { MUX_SEL_G2D0, 0 },
2412 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2418 DIV_G2D, 0, 2),
2424 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2426 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2428 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2430 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2432 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2435 7, 0, 0),
2437 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2439 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2441 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2443 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2445 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2447 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2449 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2453 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2457 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2459 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2461 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2463 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2465 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2467 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2469 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2471 0, 0, 0),
2475 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2496 #define DISP_PLL_LOCK 0x0000
2497 #define DISP_PLL_CON0 0x0100
2498 #define DISP_PLL_CON1 0x0104
2499 #define DISP_PLL_FREQ_DET 0x0108
2500 #define MUX_SEL_DISP0 0x0200
2501 #define MUX_SEL_DISP1 0x0204
2502 #define MUX_SEL_DISP2 0x0208
2503 #define MUX_SEL_DISP3 0x020c
2504 #define MUX_SEL_DISP4 0x0210
2505 #define MUX_ENABLE_DISP0 0x0300
2506 #define MUX_ENABLE_DISP1 0x0304
2507 #define MUX_ENABLE_DISP2 0x0308
2508 #define MUX_ENABLE_DISP3 0x030c
2509 #define MUX_ENABLE_DISP4 0x0310
2510 #define MUX_STAT_DISP0 0x0400
2511 #define MUX_STAT_DISP1 0x0404
2512 #define MUX_STAT_DISP2 0x0408
2513 #define MUX_STAT_DISP3 0x040c
2514 #define MUX_STAT_DISP4 0x0410
2515 #define MUX_IGNORE_DISP2 0x0508
2516 #define DIV_DISP 0x0600
2517 #define DIV_DISP_PLL_FREQ_DET 0x0604
2518 #define DIV_STAT_DISP 0x0700
2519 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2520 #define ENABLE_ACLK_DISP0 0x0800
2521 #define ENABLE_ACLK_DISP1 0x0804
2522 #define ENABLE_PCLK_DISP 0x0900
2523 #define ENABLE_SCLK_DISP 0x0a00
2524 #define ENABLE_IP_DISP0 0x0b00
2525 #define ENABLE_IP_DISP1 0x0b04
2526 #define CLKOUT_CMU_DISP 0x0c00
2527 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2559 { DISP_PLL_CON0, 0x85f40502 },
2561 { MUX_IGNORE_DISP2, 0x00111111 },
2562 { MUX_SEL_DISP0, 0 },
2563 { MUX_SEL_DISP1, 0 },
2564 { MUX_SEL_DISP2, 0 },
2565 { MUX_SEL_DISP3, 0 },
2566 { MUX_SEL_DISP4, 0 },
2626 1, 2, 0),
2628 1, 2, 0),
2633 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2634 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2637 NULL, 0, 188000000),
2639 NULL, 0, 100000000),
2642 NULL, 0, 300000000),
2644 NULL, 0, 166000000),
2650 0, 1),
2668 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2694 0, 1),
2704 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2719 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2737 DIV_DISP, 0, 2),
2743 ENABLE_ACLK_DISP0, 2, 0, 0),
2745 ENABLE_ACLK_DISP0, 0, 0, 0),
2749 ENABLE_ACLK_DISP1, 25, 0, 0),
2751 ENABLE_ACLK_DISP1, 24, 0, 0),
2753 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2755 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2757 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2759 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2761 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2763 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2765 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2767 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2769 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2771 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2773 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2776 12, CLK_IGNORE_UNUSED, 0),
2779 11, CLK_IGNORE_UNUSED, 0),
2782 10, CLK_IGNORE_UNUSED, 0),
2784 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2786 ENABLE_ACLK_DISP1, 7, 0, 0),
2788 ENABLE_ACLK_DISP1, 6, 0, 0),
2790 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2792 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2794 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2796 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2799 CLK_IGNORE_UNUSED, 0),
2802 0, CLK_IGNORE_UNUSED, 0),
2806 ENABLE_PCLK_DISP, 23, 0, 0),
2808 ENABLE_PCLK_DISP, 22, 0, 0),
2810 ENABLE_PCLK_DISP, 21, 0, 0),
2812 ENABLE_PCLK_DISP, 20, 0, 0),
2814 ENABLE_PCLK_DISP, 19, 0, 0),
2816 ENABLE_PCLK_DISP, 18, 0, 0),
2818 ENABLE_PCLK_DISP, 17, 0, 0),
2820 ENABLE_PCLK_DISP, 16, 0, 0),
2822 ENABLE_PCLK_DISP, 15, 0, 0),
2824 ENABLE_PCLK_DISP, 14, 0, 0),
2826 ENABLE_PCLK_DISP, 13, 0, 0),
2828 ENABLE_PCLK_DISP, 12, 0, 0),
2830 ENABLE_PCLK_DISP, 11, 0, 0),
2832 ENABLE_PCLK_DISP, 10, 0, 0),
2834 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2836 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2838 ENABLE_PCLK_DISP, 7, 0, 0),
2840 ENABLE_PCLK_DISP, 6, 0, 0),
2842 ENABLE_PCLK_DISP, 5, 0, 0),
2844 ENABLE_PCLK_DISP, 3, 0, 0),
2846 ENABLE_PCLK_DISP, 2, 0, 0),
2848 ENABLE_PCLK_DISP, 1, 0, 0),
2850 ENABLE_PCLK_DISP, 0, 0, 0),
2855 ENABLE_SCLK_DISP, 26, 0, 0),
2858 ENABLE_SCLK_DISP, 25, 0, 0),
2860 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2862 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2864 ENABLE_SCLK_DISP, 22, 0, 0),
2867 ENABLE_SCLK_DISP, 21, 0, 0),
2870 ENABLE_SCLK_DISP, 15, 0, 0),
2873 ENABLE_SCLK_DISP, 14, 0, 0),
2876 ENABLE_SCLK_DISP, 13, 0, 0),
2878 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2880 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2882 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2884 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2886 ENABLE_SCLK_DISP, 7, 0, 0),
2888 ENABLE_SCLK_DISP, 6, 0, 0),
2890 ENABLE_SCLK_DISP, 5, 0, 0),
2893 ENABLE_SCLK_DISP, 4, 0, 0),
2895 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2897 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2924 #define MUX_SEL_AUD0 0x0200
2925 #define MUX_SEL_AUD1 0x0204
2926 #define MUX_ENABLE_AUD0 0x0300
2927 #define MUX_ENABLE_AUD1 0x0304
2928 #define MUX_STAT_AUD0 0x0400
2929 #define DIV_AUD0 0x0600
2930 #define DIV_AUD1 0x0604
2931 #define DIV_STAT_AUD0 0x0700
2932 #define DIV_STAT_AUD1 0x0704
2933 #define ENABLE_ACLK_AUD 0x0800
2934 #define ENABLE_PCLK_AUD 0x0900
2935 #define ENABLE_SCLK_AUD0 0x0a00
2936 #define ENABLE_SCLK_AUD1 0x0a04
2937 #define ENABLE_IP_AUD0 0x0b00
2938 #define ENABLE_IP_AUD1 0x0b04
2956 { MUX_SEL_AUD0, 0 },
2957 { MUX_SEL_AUD1, 0 },
2965 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2966 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2967 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2973 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2979 MUX_SEL_AUD1, 0, 1),
2991 0, 4),
3001 DIV_AUD1, 0, 4),
3007 ENABLE_ACLK_AUD, 12, 0, 0),
3009 ENABLE_ACLK_AUD, 7, 0, 0),
3011 ENABLE_ACLK_AUD, 0, 4, 0),
3013 ENABLE_ACLK_AUD, 0, 3, 0),
3015 ENABLE_ACLK_AUD, 0, 2, 0),
3017 0, 1, 0),
3019 0, CLK_IGNORE_UNUSED, 0),
3023 13, 0, 0),
3025 12, 0, 0),
3027 11, 0, 0),
3029 ENABLE_PCLK_AUD, 10, 0, 0),
3031 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3033 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3035 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3037 ENABLE_PCLK_AUD, 6, 0, 0),
3039 ENABLE_PCLK_AUD, 5, 0, 0),
3041 ENABLE_PCLK_AUD, 4, 0, 0),
3043 ENABLE_PCLK_AUD, 3, 0, 0),
3045 2, 0, 0),
3047 ENABLE_PCLK_AUD, 0, 0, 0),
3051 2, CLK_IGNORE_UNUSED, 0),
3053 ENABLE_SCLK_AUD0, 1, 0, 0),
3055 0, 0, 0),
3059 ENABLE_SCLK_AUD1, 6, 0, 0),
3061 ENABLE_SCLK_AUD1, 5, 0, 0),
3063 ENABLE_SCLK_AUD1, 4, 0, 0),
3065 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3067 ENABLE_SCLK_AUD1, 2, 0, 0),
3069 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3071 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3092 * Register offset definitions for CMU_BUS{0|1|2}
3094 #define DIV_BUS 0x0600
3095 #define DIV_STAT_BUS 0x0700
3096 #define ENABLE_ACLK_BUS 0x0800
3097 #define ENABLE_PCLK_BUS 0x0900
3098 #define ENABLE_IP_BUS0 0x0b00
3099 #define ENABLE_IP_BUS1 0x0b04
3101 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3102 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3103 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3128 DIV_BUS, 0, 3),
3135 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3137 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3139 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3143 ENABLE_PCLK_BUS, 2, 0, 0),
3145 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3147 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3154 DIV_BUS, 0, 3),
3160 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3162 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3164 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3168 ENABLE_PCLK_BUS, 2, 0, 0),
3170 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3172 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3179 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3185 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3191 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3193 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3196 1, CLK_IGNORE_UNUSED, 0),
3199 0, CLK_IGNORE_UNUSED, 0),
3203 ENABLE_PCLK_BUS, 2, 0, 0),
3205 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3207 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3218 CMU_BUS_INFO_CLKS(0),
3246 exynos5433_cmu_bus_init(0);
3253 #define G3D_PLL_LOCK 0x0000
3254 #define G3D_PLL_CON0 0x0100
3255 #define G3D_PLL_CON1 0x0104
3256 #define G3D_PLL_FREQ_DET 0x010c
3257 #define MUX_SEL_G3D 0x0200
3258 #define MUX_ENABLE_G3D 0x0300
3259 #define MUX_STAT_G3D 0x0400
3260 #define DIV_G3D 0x0600
3261 #define DIV_G3D_PLL_FREQ_DET 0x0604
3262 #define DIV_STAT_G3D 0x0700
3263 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3264 #define ENABLE_ACLK_G3D 0x0800
3265 #define ENABLE_PCLK_G3D 0x0900
3266 #define ENABLE_SCLK_G3D 0x0a00
3267 #define ENABLE_IP_G3D0 0x0b00
3268 #define ENABLE_IP_G3D1 0x0b04
3269 #define CLKOUT_CMU_G3D 0x0c00
3270 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3271 #define CLK_STOPCTRL 0x1000
3293 { MUX_SEL_G3D, 0 },
3308 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3310 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3320 0, 3, CLK_SET_RATE_PARENT, 0),
3326 ENABLE_ACLK_G3D, 7, 0, 0),
3328 ENABLE_ACLK_G3D, 6, 0, 0),
3330 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3332 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3334 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3336 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3338 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3340 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3344 ENABLE_PCLK_G3D, 3, 0, 0),
3346 ENABLE_PCLK_G3D, 2, 0, 0),
3348 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3350 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3354 ENABLE_SCLK_G3D, 0, 0, 0),
3377 #define MUX_SEL_GSCL 0x0200
3378 #define MUX_ENABLE_GSCL 0x0300
3379 #define MUX_STAT_GSCL 0x0400
3380 #define ENABLE_ACLK_GSCL 0x0800
3381 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3382 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3383 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3384 #define ENABLE_PCLK_GSCL 0x0900
3385 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3386 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3387 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3388 #define ENABLE_IP_GSCL0 0x0b00
3389 #define ENABLE_IP_GSCL1 0x0b04
3390 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3391 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3392 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3413 { MUX_SEL_GSCL, 0 },
3414 { ENABLE_ACLK_GSCL, 0xfff },
3415 { ENABLE_PCLK_GSCL, 0xff },
3427 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3433 ENABLE_ACLK_GSCL, 11, 0, 0),
3435 ENABLE_ACLK_GSCL, 10, 0, 0),
3437 ENABLE_ACLK_GSCL, 9, 0, 0),
3440 8, CLK_IGNORE_UNUSED, 0),
3442 ENABLE_ACLK_GSCL, 7, 0, 0),
3444 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3447 CLK_IGNORE_UNUSED, 0),
3450 CLK_IGNORE_UNUSED, 0),
3452 ENABLE_ACLK_GSCL, 3, 0, 0),
3454 ENABLE_ACLK_GSCL, 2, 0, 0),
3456 ENABLE_ACLK_GSCL, 1, 0, 0),
3458 ENABLE_ACLK_GSCL, 0, 0, 0),
3462 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3466 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3470 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3474 ENABLE_PCLK_GSCL, 7, 0, 0),
3476 ENABLE_PCLK_GSCL, 6, 0, 0),
3478 ENABLE_PCLK_GSCL, 5, 0, 0),
3480 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3483 3, CLK_IGNORE_UNUSED, 0),
3485 ENABLE_PCLK_GSCL, 2, 0, 0),
3487 ENABLE_PCLK_GSCL, 1, 0, 0),
3489 ENABLE_PCLK_GSCL, 0, 0, 0),
3493 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3497 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3501 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3520 #define APOLLO_PLL_LOCK 0x0000
3521 #define APOLLO_PLL_CON0 0x0100
3522 #define APOLLO_PLL_CON1 0x0104
3523 #define APOLLO_PLL_FREQ_DET 0x010c
3524 #define MUX_SEL_APOLLO0 0x0200
3525 #define MUX_SEL_APOLLO1 0x0204
3526 #define MUX_SEL_APOLLO2 0x0208
3527 #define MUX_ENABLE_APOLLO0 0x0300
3528 #define MUX_ENABLE_APOLLO1 0x0304
3529 #define MUX_ENABLE_APOLLO2 0x0308
3530 #define MUX_STAT_APOLLO0 0x0400
3531 #define MUX_STAT_APOLLO1 0x0404
3532 #define MUX_STAT_APOLLO2 0x0408
3533 #define DIV_APOLLO0 0x0600
3534 #define DIV_APOLLO1 0x0604
3535 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3536 #define DIV_STAT_APOLLO0 0x0700
3537 #define DIV_STAT_APOLLO1 0x0704
3538 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3539 #define ENABLE_ACLK_APOLLO 0x0800
3540 #define ENABLE_PCLK_APOLLO 0x0900
3541 #define ENABLE_SCLK_APOLLO 0x0a00
3542 #define ENABLE_IP_APOLLO0 0x0b00
3543 #define ENABLE_IP_APOLLO1 0x0b04
3544 #define CLKOUT_CMU_APOLLO 0x0c00
3545 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3546 #define ARMCLK_STOPCTRL 0x1000
3547 #define APOLLO_PWR_CTRL 0x1020
3548 #define APOLLO_PWR_CTRL2 0x1024
3549 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3550 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3551 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3596 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3597 CLK_RECALC_NEW_RATES, 0),
3601 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3605 0, 1, CLK_SET_RATE_PARENT, 0),
3626 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3628 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3635 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3643 6, CLK_IGNORE_UNUSED, 0),
3646 5, CLK_IGNORE_UNUSED, 0),
3649 4, CLK_IGNORE_UNUSED, 0),
3652 3, CLK_IGNORE_UNUSED, 0),
3655 2, CLK_IGNORE_UNUSED, 0),
3658 1, CLK_IGNORE_UNUSED, 0),
3661 0, CLK_IGNORE_UNUSED, 0),
3666 2, CLK_IGNORE_UNUSED, 0),
3668 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3671 0, CLK_IGNORE_UNUSED, 0),
3675 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3677 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3685 (((hpm) << 4) | ((copy) << 0))
3698 { 0 },
3703 CLK_MOUT_BUS_PLL_APOLLO_USER, 0, 0x0,
3733 #define ATLAS_PLL_LOCK 0x0000
3734 #define ATLAS_PLL_CON0 0x0100
3735 #define ATLAS_PLL_CON1 0x0104
3736 #define ATLAS_PLL_FREQ_DET 0x010c
3737 #define MUX_SEL_ATLAS0 0x0200
3738 #define MUX_SEL_ATLAS1 0x0204
3739 #define MUX_SEL_ATLAS2 0x0208
3740 #define MUX_ENABLE_ATLAS0 0x0300
3741 #define MUX_ENABLE_ATLAS1 0x0304
3742 #define MUX_ENABLE_ATLAS2 0x0308
3743 #define MUX_STAT_ATLAS0 0x0400
3744 #define MUX_STAT_ATLAS1 0x0404
3745 #define MUX_STAT_ATLAS2 0x0408
3746 #define DIV_ATLAS0 0x0600
3747 #define DIV_ATLAS1 0x0604
3748 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3749 #define DIV_STAT_ATLAS0 0x0700
3750 #define DIV_STAT_ATLAS1 0x0704
3751 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3752 #define ENABLE_ACLK_ATLAS 0x0800
3753 #define ENABLE_PCLK_ATLAS 0x0900
3754 #define ENABLE_SCLK_ATLAS 0x0a00
3755 #define ENABLE_IP_ATLAS0 0x0b00
3756 #define ENABLE_IP_ATLAS1 0x0b04
3757 #define CLKOUT_CMU_ATLAS 0x0c00
3758 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3759 #define ARMCLK_STOPCTRL 0x1000
3760 #define ATLAS_PWR_CTRL 0x1020
3761 #define ATLAS_PWR_CTRL2 0x1024
3762 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3763 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3764 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3809 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3810 CLK_RECALC_NEW_RATES, 0),
3814 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3818 0, 1, CLK_SET_RATE_PARENT, 0),
3839 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3841 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3848 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3856 9, CLK_IGNORE_UNUSED, 0),
3859 8, CLK_IGNORE_UNUSED, 0),
3862 7, CLK_IGNORE_UNUSED, 0),
3865 6, CLK_IGNORE_UNUSED, 0),
3868 5, CLK_IGNORE_UNUSED, 0),
3871 4, CLK_IGNORE_UNUSED, 0),
3874 3, CLK_IGNORE_UNUSED, 0),
3877 2, CLK_IGNORE_UNUSED, 0),
3879 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3881 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3886 5, CLK_IGNORE_UNUSED, 0),
3889 4, CLK_IGNORE_UNUSED, 0),
3892 3, CLK_IGNORE_UNUSED, 0),
3894 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3896 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3898 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3902 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3904 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3906 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3908 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3910 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3912 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3914 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3916 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3924 (((hpm) << 4) | ((copy) << 0))
3942 { 0 },
3947 CLK_MOUT_BUS_PLL_ATLAS_USER, 0, 0x0,
3977 #define MUX_SEL_MSCL0 0x0200
3978 #define MUX_SEL_MSCL1 0x0204
3979 #define MUX_ENABLE_MSCL0 0x0300
3980 #define MUX_ENABLE_MSCL1 0x0304
3981 #define MUX_STAT_MSCL0 0x0400
3982 #define MUX_STAT_MSCL1 0x0404
3983 #define DIV_MSCL 0x0600
3984 #define DIV_STAT_MSCL 0x0700
3985 #define ENABLE_ACLK_MSCL 0x0800
3986 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3987 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3988 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3989 #define ENABLE_PCLK_MSCL 0x0900
3990 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3991 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3992 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3993 #define ENABLE_SCLK_MSCL 0x0a00
3994 #define ENABLE_IP_MSCL0 0x0b00
3995 #define ENABLE_IP_MSCL1 0x0b04
3996 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3997 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3998 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
4023 { MUX_SEL_MSCL0, 0 },
4024 { MUX_SEL_MSCL1, 0 },
4038 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4042 MUX_SEL_MSCL1, 0, 1),
4048 DIV_MSCL, 0, 3),
4054 ENABLE_ACLK_MSCL, 9, 0, 0),
4056 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4058 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4060 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4062 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4064 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4066 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4068 ENABLE_ACLK_MSCL, 2, 0, 0),
4070 ENABLE_ACLK_MSCL, 1, 0, 0),
4072 ENABLE_ACLK_MSCL, 0, 0, 0),
4078 0, CLK_IGNORE_UNUSED, 0),
4084 0, CLK_IGNORE_UNUSED, 0),
4089 0, CLK_IGNORE_UNUSED, 0),
4093 ENABLE_PCLK_MSCL, 7, 0, 0),
4095 ENABLE_PCLK_MSCL, 6, 0, 0),
4097 ENABLE_PCLK_MSCL, 5, 0, 0),
4099 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4101 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4103 ENABLE_PCLK_MSCL, 2, 0, 0),
4105 ENABLE_PCLK_MSCL, 1, 0, 0),
4107 ENABLE_PCLK_MSCL, 0, 0, 0),
4112 0, CLK_IGNORE_UNUSED, 0),
4117 0, CLK_IGNORE_UNUSED, 0),
4122 0, CLK_IGNORE_UNUSED, 0),
4125 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4126 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4147 #define MUX_SEL_MFC 0x0200
4148 #define MUX_ENABLE_MFC 0x0300
4149 #define MUX_STAT_MFC 0x0400
4150 #define DIV_MFC 0x0600
4151 #define DIV_STAT_MFC 0x0700
4152 #define ENABLE_ACLK_MFC 0x0800
4153 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4154 #define ENABLE_PCLK_MFC 0x0900
4155 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4156 #define ENABLE_IP_MFC0 0x0b00
4157 #define ENABLE_IP_MFC1 0x0b04
4158 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4174 { MUX_SEL_MFC, 0 },
4182 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4188 DIV_MFC, 0, 2),
4194 ENABLE_ACLK_MFC, 6, 0, 0),
4196 ENABLE_ACLK_MFC, 5, 0, 0),
4198 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4200 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4202 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4204 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4206 ENABLE_ACLK_MFC, 0, 0, 0),
4211 1, CLK_IGNORE_UNUSED, 0),
4214 0, CLK_IGNORE_UNUSED, 0),
4218 ENABLE_PCLK_MFC, 4, 0, 0),
4220 ENABLE_PCLK_MFC, 3, 0, 0),
4222 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4224 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4226 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4231 1, CLK_IGNORE_UNUSED, 0),
4234 0, CLK_IGNORE_UNUSED, 0),
4255 #define MUX_SEL_HEVC 0x0200
4256 #define MUX_ENABLE_HEVC 0x0300
4257 #define MUX_STAT_HEVC 0x0400
4258 #define DIV_HEVC 0x0600
4259 #define DIV_STAT_HEVC 0x0700
4260 #define ENABLE_ACLK_HEVC 0x0800
4261 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4262 #define ENABLE_PCLK_HEVC 0x0900
4263 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4264 #define ENABLE_IP_HEVC0 0x0b00
4265 #define ENABLE_IP_HEVC1 0x0b04
4266 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4282 { MUX_SEL_HEVC, 0 },
4290 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4296 DIV_HEVC, 0, 2),
4302 ENABLE_ACLK_HEVC, 6, 0, 0),
4304 ENABLE_ACLK_HEVC, 5, 0, 0),
4306 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4308 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4310 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4312 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4314 ENABLE_ACLK_HEVC, 0, 0, 0),
4320 1, CLK_IGNORE_UNUSED, 0),
4324 0, CLK_IGNORE_UNUSED, 0),
4328 ENABLE_PCLK_HEVC, 4, 0, 0),
4330 ENABLE_PCLK_HEVC, 3, 0, 0),
4332 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4334 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4336 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4341 1, CLK_IGNORE_UNUSED, 0),
4344 0, CLK_IGNORE_UNUSED, 0),
4365 #define MUX_SEL_ISP 0x0200
4366 #define MUX_ENABLE_ISP 0x0300
4367 #define MUX_STAT_ISP 0x0400
4368 #define DIV_ISP 0x0600
4369 #define DIV_STAT_ISP 0x0700
4370 #define ENABLE_ACLK_ISP0 0x0800
4371 #define ENABLE_ACLK_ISP1 0x0804
4372 #define ENABLE_ACLK_ISP2 0x0808
4373 #define ENABLE_PCLK_ISP 0x0900
4374 #define ENABLE_SCLK_ISP 0x0a00
4375 #define ENABLE_IP_ISP0 0x0b00
4376 #define ENABLE_IP_ISP1 0x0b04
4377 #define ENABLE_IP_ISP2 0x0b08
4378 #define ENABLE_IP_ISP3 0x0b0c
4396 { MUX_SEL_ISP, 0 },
4405 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4407 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4419 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4425 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4427 ENABLE_ACLK_ISP0, 5, 0, 0),
4429 ENABLE_ACLK_ISP0, 4, 0, 0),
4431 ENABLE_ACLK_ISP0, 3, 0, 0),
4433 ENABLE_ACLK_ISP0, 2, 0, 0),
4435 ENABLE_ACLK_ISP0, 1, 0, 0),
4437 ENABLE_ACLK_ISP0, 0, 0, 0),
4442 17, CLK_IGNORE_UNUSED, 0),
4445 16, CLK_IGNORE_UNUSED, 0),
4448 15, CLK_IGNORE_UNUSED, 0),
4451 14, CLK_IGNORE_UNUSED, 0),
4454 13, CLK_IGNORE_UNUSED, 0),
4457 12, CLK_IGNORE_UNUSED, 0),
4460 11, CLK_IGNORE_UNUSED, 0),
4463 10, CLK_IGNORE_UNUSED, 0),
4466 9, CLK_IGNORE_UNUSED, 0),
4469 8, CLK_IGNORE_UNUSED, 0),
4472 7, CLK_IGNORE_UNUSED, 0),
4474 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4476 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4479 4, CLK_IGNORE_UNUSED, 0),
4482 3, CLK_IGNORE_UNUSED, 0),
4484 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4486 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4488 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4493 13, CLK_IGNORE_UNUSED, 0),
4495 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4497 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4499 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4502 9, CLK_IGNORE_UNUSED, 0),
4504 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4506 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4509 6, CLK_IGNORE_UNUSED, 0),
4511 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4513 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4515 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4518 2, CLK_IGNORE_UNUSED, 0),
4520 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4522 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4526 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4528 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4530 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4532 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4534 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4536 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4538 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4540 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4542 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4544 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4546 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4548 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4550 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4552 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4554 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4556 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4558 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4560 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4563 7, CLK_IGNORE_UNUSED, 0),
4565 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4567 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4569 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4571 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4573 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4575 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4577 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4582 5, CLK_IGNORE_UNUSED, 0),
4585 4, CLK_IGNORE_UNUSED, 0),
4588 3, CLK_IGNORE_UNUSED, 0),
4591 2, CLK_IGNORE_UNUSED, 0),
4594 1, CLK_IGNORE_UNUSED, 0),
4597 0, CLK_IGNORE_UNUSED, 0),
4618 #define MUX_SEL_CAM00 0x0200
4619 #define MUX_SEL_CAM01 0x0204
4620 #define MUX_SEL_CAM02 0x0208
4621 #define MUX_SEL_CAM03 0x020c
4622 #define MUX_SEL_CAM04 0x0210
4623 #define MUX_ENABLE_CAM00 0x0300
4624 #define MUX_ENABLE_CAM01 0x0304
4625 #define MUX_ENABLE_CAM02 0x0308
4626 #define MUX_ENABLE_CAM03 0x030c
4627 #define MUX_ENABLE_CAM04 0x0310
4628 #define MUX_STAT_CAM00 0x0400
4629 #define MUX_STAT_CAM01 0x0404
4630 #define MUX_STAT_CAM02 0x0408
4631 #define MUX_STAT_CAM03 0x040c
4632 #define MUX_STAT_CAM04 0x0410
4633 #define MUX_IGNORE_CAM01 0x0504
4634 #define DIV_CAM00 0x0600
4635 #define DIV_CAM01 0x0604
4636 #define DIV_CAM02 0x0608
4637 #define DIV_CAM03 0x060c
4638 #define DIV_STAT_CAM00 0x0700
4639 #define DIV_STAT_CAM01 0x0704
4640 #define DIV_STAT_CAM02 0x0708
4641 #define DIV_STAT_CAM03 0x070c
4642 #define ENABLE_ACLK_CAM00 0X0800
4643 #define ENABLE_ACLK_CAM01 0X0804
4644 #define ENABLE_ACLK_CAM02 0X0808
4645 #define ENABLE_PCLK_CAM0 0X0900
4646 #define ENABLE_SCLK_CAM0 0X0a00
4647 #define ENABLE_IP_CAM00 0X0b00
4648 #define ENABLE_IP_CAM01 0X0b04
4649 #define ENABLE_IP_CAM02 0X0b08
4650 #define ENABLE_IP_CAM03 0X0b0C
4680 { MUX_SEL_CAM00, 0 },
4681 { MUX_SEL_CAM01, 0 },
4682 { MUX_SEL_CAM02, 0 },
4683 { MUX_SEL_CAM03, 0 },
4684 { MUX_SEL_CAM04, 0 },
4747 NULL, 0, 100000000),
4749 NULL, 0, 100000000),
4759 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4769 MUX_SEL_CAM01, 0, 1),
4785 MUX_SEL_CAM02, 0, 1),
4803 MUX_SEL_CAM03, 0, 1),
4823 MUX_SEL_CAM04, 0, 1),
4833 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4847 DIV_CAM01, 0, 3),
4861 DIV_CAM02, 0, 3),
4870 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4876 6, 0, 0),
4878 5, 0, 0),
4880 4, 0, 0),
4882 3, 0, 0),
4884 ENABLE_ACLK_CAM00, 2, 0, 0),
4886 ENABLE_ACLK_CAM00, 1, 0, 0),
4888 ENABLE_ACLK_CAM00, 0, 0, 0),
4892 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4894 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4896 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4898 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4900 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4902 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4904 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4906 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4909 23, CLK_IGNORE_UNUSED, 0),
4912 22, CLK_IGNORE_UNUSED, 0),
4915 21, CLK_IGNORE_UNUSED, 0),
4918 20, CLK_IGNORE_UNUSED, 0),
4921 19, CLK_IGNORE_UNUSED, 0),
4924 18, CLK_IGNORE_UNUSED, 0),
4927 17, CLK_IGNORE_UNUSED, 0),
4930 16, CLK_IGNORE_UNUSED, 0),
4933 15, CLK_IGNORE_UNUSED, 0),
4936 14, CLK_IGNORE_UNUSED, 0),
4939 13, CLK_IGNORE_UNUSED, 0),
4942 12, CLK_IGNORE_UNUSED, 0),
4945 11, CLK_IGNORE_UNUSED, 0),
4948 10, CLK_IGNORE_UNUSED, 0),
4951 9, CLK_IGNORE_UNUSED, 0),
4954 8, CLK_IGNORE_UNUSED, 0),
4957 7, CLK_IGNORE_UNUSED, 0),
4960 6, CLK_IGNORE_UNUSED, 0),
4962 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4964 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4966 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4968 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4970 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4972 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4976 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4978 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4980 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4982 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4984 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4986 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4988 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4990 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4992 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4994 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4998 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
5000 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
5002 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
5004 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
5006 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
5008 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
5010 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
5012 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
5014 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
5016 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
5018 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
5020 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
5022 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
5025 12, CLK_IGNORE_UNUSED, 0),
5028 11, CLK_IGNORE_UNUSED, 0),
5031 10, CLK_IGNORE_UNUSED, 0),
5033 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5035 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5038 7, CLK_IGNORE_UNUSED, 0),
5040 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5042 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5044 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5046 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5048 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5050 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5052 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5057 ENABLE_SCLK_CAM0, 8, 0, 0),
5060 ENABLE_SCLK_CAM0, 7, 0, 0),
5062 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5064 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5066 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5068 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5071 ENABLE_SCLK_CAM0, 2, 0, 0),
5074 ENABLE_SCLK_CAM0, 1, 0, 0),
5077 ENABLE_SCLK_CAM0, 0, 0, 0),
5100 #define MUX_SEL_CAM10 0x0200
5101 #define MUX_SEL_CAM11 0x0204
5102 #define MUX_SEL_CAM12 0x0208
5103 #define MUX_ENABLE_CAM10 0x0300
5104 #define MUX_ENABLE_CAM11 0x0304
5105 #define MUX_ENABLE_CAM12 0x0308
5106 #define MUX_STAT_CAM10 0x0400
5107 #define MUX_STAT_CAM11 0x0404
5108 #define MUX_STAT_CAM12 0x0408
5109 #define MUX_IGNORE_CAM11 0x0504
5110 #define DIV_CAM10 0x0600
5111 #define DIV_CAM11 0x0604
5112 #define DIV_STAT_CAM10 0x0700
5113 #define DIV_STAT_CAM11 0x0704
5114 #define ENABLE_ACLK_CAM10 0X0800
5115 #define ENABLE_ACLK_CAM11 0X0804
5116 #define ENABLE_ACLK_CAM12 0X0808
5117 #define ENABLE_PCLK_CAM1 0X0900
5118 #define ENABLE_SCLK_CAM1 0X0a00
5119 #define ENABLE_IP_CAM10 0X0b00
5120 #define ENABLE_IP_CAM11 0X0b04
5121 #define ENABLE_IP_CAM12 0X0b08
5144 { MUX_SEL_CAM10, 0 },
5145 { MUX_SEL_CAM11, 0 },
5146 { MUX_SEL_CAM12, 0 },
5177 0, 100000000),
5193 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5199 MUX_SEL_CAM11, 0, 1),
5213 MUX_SEL_CAM12, 0, 1),
5227 DIV_CAM10, 0, 3),
5237 DIV_CAM11, 0, 3),
5243 ENABLE_ACLK_CAM10, 4, 0, 0),
5245 ENABLE_ACLK_CAM10, 3, 0, 0),
5247 ENABLE_ACLK_CAM10, 1, 0, 0),
5249 ENABLE_ACLK_CAM10, 0, 0, 0),
5253 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5255 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5258 27, CLK_IGNORE_UNUSED, 0),
5261 26, CLK_IGNORE_UNUSED, 0),
5264 25, CLK_IGNORE_UNUSED, 0),
5267 24, CLK_IGNORE_UNUSED, 0),
5270 23, CLK_IGNORE_UNUSED, 0),
5273 22, CLK_IGNORE_UNUSED, 0),
5276 21, CLK_IGNORE_UNUSED, 0),
5279 20, CLK_IGNORE_UNUSED, 0),
5282 19, CLK_IGNORE_UNUSED, 0),
5285 18, CLK_IGNORE_UNUSED, 0),
5288 17, CLK_IGNORE_UNUSED, 0),
5291 16, CLK_IGNORE_UNUSED, 0),
5294 15, CLK_IGNORE_UNUSED, 0),
5296 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5299 13, CLK_IGNORE_UNUSED, 0),
5302 12, CLK_IGNORE_UNUSED, 0),
5304 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5306 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5309 9, CLK_IGNORE_UNUSED, 0),
5311 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5313 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5315 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5317 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5319 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5321 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5323 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5325 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5327 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5332 10, CLK_IGNORE_UNUSED, 0),
5334 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5337 8, CLK_IGNORE_UNUSED, 0),
5339 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5341 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5343 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5346 4, CLK_IGNORE_UNUSED, 0),
5349 3, CLK_IGNORE_UNUSED, 0),
5352 2, CLK_IGNORE_UNUSED, 0),
5354 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5357 0, CLK_IGNORE_UNUSED, 0),
5361 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5363 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5365 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5367 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5369 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5371 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5373 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5376 20, CLK_IGNORE_UNUSED, 0),
5379 19, CLK_IGNORE_UNUSED, 0),
5381 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5384 17, CLK_IGNORE_UNUSED, 0),
5386 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5388 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5391 14, CLK_IGNORE_UNUSED, 0),
5393 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5395 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5397 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5399 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5401 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5403 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5405 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5407 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5409 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5411 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5413 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5415 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5417 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5419 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5423 15, 0, 0),
5425 14, 0, 0),
5427 13, 0, 0),
5429 12, 0, 0),
5432 ENABLE_SCLK_CAM1, 11, 0, 0),
5434 ENABLE_SCLK_CAM1, 10, 0, 0),
5436 ENABLE_SCLK_CAM1, 9, 0, 0),
5438 ENABLE_SCLK_CAM1, 7, 0, 0),
5440 ENABLE_SCLK_CAM1, 6, 0, 0),
5442 ENABLE_SCLK_CAM1, 5, 0, 0),
5444 ENABLE_SCLK_CAM1, 4, 0, 0),
5446 ENABLE_SCLK_CAM1, 3, 0, 0),
5448 ENABLE_SCLK_CAM1, 2, 0, 0),
5450 ENABLE_SCLK_CAM1, 1, 0, 0),
5452 ENABLE_SCLK_CAM1, 0, 0, 0),
5475 #define ENABLE_ACLK_IMEM_SLIMSSS 0x080c
5476 #define ENABLE_PCLK_IMEM_SLIMSSS 0x0908
5486 ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5490 ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),