Lines Matching +full:rtic +full:-

1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos5420.h>
12 #include <linux/clk-provider.h>
18 #include "clk-cpu.h"
19 #include "clk-exynos5-subcmu.h"
897 	/* Audio - I2S */
904 	/* SPI Pre-Ratio */
1041 	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1438 	PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1441 	PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1448 	PLL_36XX_RATE(24 * MHZ,  49152000U, 197, 3, 5, -25690),
1572 	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1594 	hws = ctx->clk_data.hws;  in exynos5x_clk_init()
1671 	clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);  in exynos5x_clk_init()
1676 	clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);  in exynos5x_clk_init()
1685 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
1692 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",