Lines Matching +full:pd +full:- +full:samsung
1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2018 Samsung Electronics Co., Ltd.
4 // Author: Marek Szyprowski <m.szyprowski@samsung.com>
5 // Common Clock Framework support for Exynos5 power-domain dependent clocks
15 #include "clk-exynos5-subcmu.h"
25 for (; num_regs > 0; --num_regs, ++rd) {
26 rd->save = readl(base + rd->offset);
27 writel((rd->save & ~rd->mask) | rd->value, base + rd->offset);
28 rd->save &= rd->mask;
36 for (; num_regs > 0; --num_regs, ++rd)
37 writel((readl(base + rd->offset) & ~rd->mask) | rd->save,
38 base + rd->offset);
44 while (nr_clk--)
45 samsung_clk_add_lookup(ctx, ERR_PTR(-EPROBE_DEFER), list++->id);
49 * Pass the needed clock provider context and register sub-CMU clocks
51 * NOTE: This function has to be called from the main, CLK_OF_DECLARE-
54 * drivers: one which binds to the same device-tree node as CLK_OF_DECLARE
55 * driver and second, for handling its per-domain child-devices. Those
57 * when OF-core populates all device-tree nodes.
66 for (; _nr_cmus--; _cmu++) {
67 exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,
68 (*_cmu)->nr_gate_clks);
69 exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,
70 (*_cmu)->nr_suspend_regs);
79 spin_lock_irqsave(&ctx->lock, flags);
80 exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs,
81 info->nr_suspend_regs);
82 spin_unlock_irqrestore(&ctx->lock, flags);
92 spin_lock_irqsave(&ctx->lock, flags);
93 exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs,
94 info->nr_suspend_regs);
95 spin_unlock_irqrestore(&ctx->lock, flags);
102 struct device *dev = &pdev->dev;
109 ctx->dev = dev;
110 samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks);
111 samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks);
112 ctx->dev = NULL;
128 .name = "exynos5-subcmu",
143 pdev = platform_device_alloc("exynos5-subcmu", PLATFORM_DEVID_AUTO);
145 return -ENOMEM;
147 pdev->dev.parent = parent;
149 of_genpd_add_device(&genpdspec, &pdev->dev);
163 for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
167 if (strcmp(cmu[i]->pd_name, name) == 0)
168 exynos5_clk_register_subcmu(&pdev->dev,
175 { .compatible = "samsung,exynos5250-clock", },
176 { .compatible = "samsung,exynos5420-clock", },
177 { .compatible = "samsung,exynos5800-clock", },
183 .name = "exynos5-clock",