Lines Matching +full:exynos4210 +full:- +full:chipid

1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos4.h>
13 #include <linux/clk-provider.h>
19 #include "clk-cpu.h"
143 	EXYNOS4210,  enumerator
299 /* Exynos 4210-specific parent groups */
338 /* Exynos 4x12-specific parent groups */
442 /* list of mux clocks supported in exynos4210 soc */
682 /* list of divider clocks supported in exynos4210 soc */
878 	GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
916 /* list of gate clocks supported in exynos4210 soc */
934 	GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
976 	GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
1015  * resides in chipid register space, outside of the clock controller memory
1016  * mapped space. So to determine the parent of fin_pll clock, the chipid
1026 	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");  in exynos4_get_xom()
1051 	finpll_f = clk_hw_get_rate(ctx->clk_data.hws[parent]);  in exynos4_clk_register_finpll()
1069 	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
1070 	{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1129 	PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
1286 	hws = ctx->clk_data.hws;  in exynos4_clk_init()
1294 	if (exynos4_soc == EXYNOS4210) {  in exynos4_clk_init()
1336 	if (exynos4_soc == EXYNOS4210) {  in exynos4_clk_init()
1374 	if (exynos4_soc == EXYNOS4210)  in exynos4_clk_init()
1386 		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",  in exynos4_clk_init()
1397 	exynos4_clk_init(np, EXYNOS4210);  in exynos4210_clk_init()
1399 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
1405 CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init);
1411 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);