Lines Matching +full:0 +full:x10300
22 #define SRC_LEFTBUS 0x4200
23 #define DIV_LEFTBUS 0x4500
24 #define GATE_IP_LEFTBUS 0x4800
25 #define E4X12_GATE_IP_IMAGE 0x4930
26 #define CLKOUT_CMU_LEFTBUS 0x4a00
27 #define SRC_RIGHTBUS 0x8200
28 #define DIV_RIGHTBUS 0x8500
29 #define GATE_IP_RIGHTBUS 0x8800
30 #define E4X12_GATE_IP_PERIR 0x8960
31 #define CLKOUT_CMU_RIGHTBUS 0x8a00
32 #define EPLL_LOCK 0xc010
33 #define VPLL_LOCK 0xc020
34 #define EPLL_CON0 0xc110
35 #define EPLL_CON1 0xc114
36 #define EPLL_CON2 0xc118
37 #define VPLL_CON0 0xc120
38 #define VPLL_CON1 0xc124
39 #define VPLL_CON2 0xc128
40 #define SRC_TOP0 0xc210
41 #define SRC_TOP1 0xc214
42 #define SRC_CAM 0xc220
43 #define SRC_TV 0xc224
44 #define SRC_MFC 0xc228
45 #define SRC_G3D 0xc22c
46 #define E4210_SRC_IMAGE 0xc230
47 #define SRC_LCD0 0xc234
48 #define E4210_SRC_LCD1 0xc238
49 #define E4X12_SRC_ISP 0xc238
50 #define SRC_MAUDIO 0xc23c
51 #define SRC_FSYS 0xc240
52 #define SRC_PERIL0 0xc250
53 #define SRC_PERIL1 0xc254
54 #define E4X12_SRC_CAM1 0xc258
55 #define SRC_MASK_TOP 0xc310
56 #define SRC_MASK_CAM 0xc320
57 #define SRC_MASK_TV 0xc324
58 #define SRC_MASK_LCD0 0xc334
59 #define E4210_SRC_MASK_LCD1 0xc338
60 #define E4X12_SRC_MASK_ISP 0xc338
61 #define SRC_MASK_MAUDIO 0xc33c
62 #define SRC_MASK_FSYS 0xc340
63 #define SRC_MASK_PERIL0 0xc350
64 #define SRC_MASK_PERIL1 0xc354
65 #define DIV_TOP 0xc510
66 #define DIV_CAM 0xc520
67 #define DIV_TV 0xc524
68 #define DIV_MFC 0xc528
69 #define DIV_G3D 0xc52c
70 #define DIV_IMAGE 0xc530
71 #define DIV_LCD0 0xc534
72 #define E4210_DIV_LCD1 0xc538
73 #define E4X12_DIV_ISP 0xc538
74 #define DIV_MAUDIO 0xc53c
75 #define DIV_FSYS0 0xc540
76 #define DIV_FSYS1 0xc544
77 #define DIV_FSYS2 0xc548
78 #define DIV_FSYS3 0xc54c
79 #define DIV_PERIL0 0xc550
80 #define DIV_PERIL1 0xc554
81 #define DIV_PERIL2 0xc558
82 #define DIV_PERIL3 0xc55c
83 #define DIV_PERIL4 0xc560
84 #define DIV_PERIL5 0xc564
85 #define E4X12_DIV_CAM1 0xc568
86 #define E4X12_GATE_BUS_FSYS1 0xc744
87 #define GATE_SCLK_CAM 0xc820
88 #define GATE_IP_CAM 0xc920
89 #define GATE_IP_TV 0xc924
90 #define GATE_IP_MFC 0xc928
91 #define GATE_IP_G3D 0xc92c
92 #define E4210_GATE_IP_IMAGE 0xc930
93 #define GATE_IP_LCD0 0xc934
94 #define E4210_GATE_IP_LCD1 0xc938
95 #define E4X12_GATE_IP_ISP 0xc938
96 #define E4X12_GATE_IP_MAUDIO 0xc93c
97 #define GATE_IP_FSYS 0xc940
98 #define GATE_IP_GPS 0xc94c
99 #define GATE_IP_PERIL 0xc950
100 #define E4210_GATE_IP_PERIR 0xc960
101 #define GATE_BLOCK 0xc970
102 #define CLKOUT_CMU_TOP 0xca00
103 #define E4X12_MPLL_LOCK 0x10008
104 #define E4X12_MPLL_CON0 0x10108
105 #define SRC_DMC 0x10200
106 #define SRC_MASK_DMC 0x10300
107 #define DIV_DMC0 0x10500
108 #define DIV_DMC1 0x10504
109 #define GATE_IP_DMC 0x10900
110 #define CLKOUT_CMU_DMC 0x10a00
111 #define APLL_LOCK 0x14000
112 #define E4210_MPLL_LOCK 0x14008
113 #define APLL_CON0 0x14100
114 #define E4210_MPLL_CON0 0x14108
115 #define SRC_CPU 0x14200
116 #define DIV_CPU0 0x14500
117 #define DIV_CPU1 0x14504
118 #define GATE_SCLK_CPU 0x14800
119 #define GATE_IP_CPU 0x14900
120 #define CLKOUT_CMU_CPU 0x14a00
121 #define PWR_CTRL1 0x15020
122 #define E4X12_PWR_CTRL2 0x15024
125 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
126 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
136 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
265 { .offset = VPLL_CON0, .value = 0x80600302, },
266 { .offset = EPLL_CON0, .value = 0x806F0302, },
267 { .offset = SRC_MASK_TOP, .value = 0x00000001, },
268 { .offset = SRC_MASK_CAM, .value = 0x11111111, },
269 { .offset = SRC_MASK_TV, .value = 0x00000111, },
270 { .offset = SRC_MASK_LCD0, .value = 0x00001111, },
271 { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
272 { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
273 { .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
274 { .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
275 { .offset = SRC_MASK_DMC, .value = 0x00010000, },
279 { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
389 FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
390 FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
395 FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
396 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
397 FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
401 FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
405 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
406 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
407 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
408 FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
412 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
416 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
417 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
418 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
419 FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
424 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
425 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
426 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
427 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
428 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
430 CLK_SET_RATE_PARENT, 0),
432 CLK_SET_RATE_PARENT, 0),
433 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
434 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
436 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
438 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
439 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
444 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
448 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
449 MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
450 CLKOUT_CMU_LEFTBUS, 0, 5),
452 MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
453 MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
454 CLKOUT_CMU_RIGHTBUS, 0, 5),
456 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
457 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
458 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
459 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
461 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
462 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
463 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
464 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
465 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
466 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
469 MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
471 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
479 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
480 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
481 CLK_SET_RATE_PARENT, 0),
482 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
483 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
484 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
485 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
486 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
487 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
488 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
489 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
490 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
491 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
492 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
493 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
494 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
495 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
496 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
497 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
498 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
499 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
500 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
501 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
503 MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
504 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
506 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
511 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
512 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
513 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
514 CLKOUT_CMU_LEFTBUS, 0, 5),
516 MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
517 MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
518 MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
519 CLKOUT_CMU_RIGHTBUS, 0, 5),
523 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
525 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
526 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
529 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
534 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
535 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
536 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
537 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
538 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
539 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
540 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
541 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
542 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
543 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
547 MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
548 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
556 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
557 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
558 CLK_SET_RATE_PARENT, 0),
559 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
560 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
561 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
562 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
563 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
564 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
565 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
566 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
567 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
568 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
569 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
570 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
571 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
572 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
573 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
574 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
575 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
576 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
577 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
578 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
579 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
580 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
581 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
582 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
584 MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
585 MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
586 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
587 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
588 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
589 MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
594 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
595 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
596 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
599 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
600 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
601 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
604 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
605 DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
606 DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
607 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
608 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
609 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
611 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
612 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
613 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
615 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
616 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
617 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
618 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
619 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
620 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
621 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
622 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
623 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
624 DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
625 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
626 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
627 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
629 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
630 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
631 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
632 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
633 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
637 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
641 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
643 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
644 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
645 CLK_SET_RATE_PARENT, 0),
646 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
647 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
648 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
649 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
650 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
651 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
652 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
653 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
654 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
655 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
656 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
657 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
658 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
660 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
661 CLK_SET_RATE_PARENT, 0),
662 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
663 CLK_SET_RATE_PARENT, 0),
664 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
665 CLK_SET_RATE_PARENT, 0),
666 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
667 CLK_SET_RATE_PARENT, 0),
668 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
669 CLK_SET_RATE_PARENT, 0),
670 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
672 DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
673 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
674 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
676 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
677 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
678 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
679 DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
684 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
685 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
686 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
687 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
688 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
689 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
690 CLK_SET_RATE_PARENT, 0),
695 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
696 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
697 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
698 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
699 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
700 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
701 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
704 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
705 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
706 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
707 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
708 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
709 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
710 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
712 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
717 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
718 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
719 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
720 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
721 0),
722 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
723 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
724 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
725 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
726 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
727 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
728 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
729 0),
730 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
731 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
732 GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
733 GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
734 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
735 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
736 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
737 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
738 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
739 GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
740 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
742 CLK_SET_RATE_PARENT, 0),
744 CLK_SET_RATE_PARENT, 0),
746 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
747 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
748 CLK_SET_RATE_PARENT, 0),
749 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
750 CLK_SET_RATE_PARENT, 0),
751 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
752 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
753 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
754 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
755 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
756 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
757 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
758 CLK_SET_RATE_PARENT, 0),
760 CLK_SET_RATE_PARENT, 0),
762 CLK_SET_RATE_PARENT, 0),
764 CLK_SET_RATE_PARENT, 0),
766 CLK_SET_RATE_PARENT, 0),
768 CLK_SET_RATE_PARENT, 0),
769 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
770 CLK_SET_RATE_PARENT, 0),
771 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
772 CLK_SET_RATE_PARENT, 0),
774 CLK_SET_RATE_PARENT, 0),
776 CLK_SET_RATE_PARENT, 0),
778 CLK_SET_RATE_PARENT, 0),
780 CLK_SET_RATE_PARENT, 0),
781 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
782 CLK_SET_RATE_PARENT, 0),
784 CLK_SET_RATE_PARENT, 0),
786 CLK_SET_RATE_PARENT, 0),
788 CLK_SET_RATE_PARENT, 0),
790 CLK_SET_RATE_PARENT, 0),
792 CLK_SET_RATE_PARENT, 0),
794 CLK_SET_RATE_PARENT, 0),
796 CLK_SET_RATE_PARENT, 0),
798 CLK_SET_RATE_PARENT, 0),
799 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
800 0, 0),
802 0, 0),
804 0, 0),
806 0, 0),
808 0, 0),
810 0, 0),
812 0, 0),
814 0, 0),
816 0, 0),
818 0, 0),
820 0, 0),
821 GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
822 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
823 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
825 0, 0),
826 GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
827 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
829 0, 0),
831 0, 0),
832 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
833 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
834 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
835 0, 0),
837 0, 0),
838 GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
839 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
840 0, 0),
842 0, 0),
844 0, 0),
846 0, 0),
848 0, 0),
850 0, 0),
851 GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
852 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
853 0, 0),
855 0, 0),
857 0, 0),
859 0, 0),
861 0, 0),
863 0, 0),
865 0, 0),
867 0, 0),
869 0, 0),
871 0, 0),
873 0, 0),
875 0, 0),
877 0, 0),
879 0, 0),
881 0, 0),
883 0, 0),
885 0, 0),
887 0, 0),
889 0, 0),
891 0, 0),
893 0, 0),
895 0, 0),
897 0, 0),
898 GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
899 GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
900 GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
901 GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
902 GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
905 CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
907 CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
909 CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
911 CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
913 CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
918 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
919 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
920 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
921 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
922 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
923 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
924 0),
925 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
926 0),
927 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
928 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
929 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
930 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
931 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
932 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
933 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
934 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
935 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
936 CLK_IGNORE_UNUSED, 0),
937 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
938 0),
940 E4210_GATE_IP_IMAGE, 4, 0, 0),
942 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
944 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
945 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
946 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
948 0, 0),
950 0, 0),
952 0, 0),
954 0, 0),
956 0, 0),
957 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
958 CLK_SET_RATE_PARENT, 0),
959 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
960 0),
965 GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0),
966 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
967 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
968 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
969 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
970 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
971 0),
972 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
973 0),
974 GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
975 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
976 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
978 CLK_IGNORE_UNUSED, 0),
979 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
980 0),
982 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
984 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
986 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
988 E4X12_GATE_IP_IMAGE, 4, 0, 0),
990 0, 0),
992 0, 0),
993 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
995 E4X12_GATE_IP_ISP, 0, 0, 0),
997 E4X12_GATE_IP_ISP, 1, 0, 0),
999 E4X12_GATE_IP_ISP, 2, 0, 0),
1001 E4X12_GATE_IP_ISP, 3, 0, 0),
1002 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
1004 0, 0),
1006 0, 0),
1007 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
1008 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
1009 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
1010 0),
1014 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1017 * controller is first remapped and the value of XOM[0] bit is read to
1022 unsigned long xom = 0; in exynos4_get_xom()
1028 chipid_base = of_iomap(np, 0); in exynos4_get_xom()
1062 fclk.flags = 0; in exynos4_clk_register_finpll()
1069 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
1089 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
1090 PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
1091 PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0),
1094 PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0),
1095 PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0),
1100 PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
1102 PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
1103 PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
1104 PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0),
1109 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1110 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1111 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1112 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1113 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1114 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1115 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1116 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1117 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
1118 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
1130 PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
1132 PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),
1142 PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0),
1143 PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0),
1144 PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0),
1145 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
1194 writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2); in exynos4x12_core_down_clock()
1201 (((hpm) << 4) | ((copy) << 0))
1204 { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
1205 { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
1206 { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1207 { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1208 { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1209 { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
1210 { 0 },
1214 { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
1215 { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
1216 { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
1217 { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
1218 { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
1219 { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
1220 { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
1221 { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
1222 { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1223 { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1224 { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1225 { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1226 { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1227 { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
1228 { 0 },
1232 (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
1235 { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
1236 { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
1237 { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
1238 { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
1239 { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
1240 { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
1241 { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
1242 { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
1243 { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
1244 { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
1245 { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
1246 { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
1247 { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
1248 { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
1249 { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
1250 { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
1251 { 0 },
1256 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
1262 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
1268 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
1281 reg_base = of_iomap(np, 0); in exynos4_clk_init()