Lines Matching refs:mux_sel
59 u32 mux_sel; member
187 .mux_sel = 0x200,
223 if (readl(base + regs->mux_sel) & E4210_MUX_HPM_MASK) in exynos_cpuclk_pre_rate_change()
256 mux_reg = readl(base + regs->mux_sel); in exynos_cpuclk_pre_rate_change()
257 writel(mux_reg | (1 << 16), base + regs->mux_sel); in exynos_cpuclk_pre_rate_change()
297 mux_reg = readl(base + regs->mux_sel); in exynos_cpuclk_post_rate_change()
298 writel(mux_reg & ~(1 << 16), base + regs->mux_sel); in exynos_cpuclk_post_rate_change()
314 .mux_sel = 0x208,
369 mux_reg = readl(base + regs->mux_sel); in exynos5433_cpuclk_pre_rate_change()
370 writel(mux_reg | 1, base + regs->mux_sel); in exynos5433_cpuclk_pre_rate_change()
397 mux_reg = readl(base + regs->mux_sel); in exynos5433_cpuclk_post_rate_change()
398 writel(mux_reg & ~1, base + regs->mux_sel); in exynos5433_cpuclk_post_rate_change()