Lines Matching full:alternate

28  * alternate clock source. If required, the alternate clock source is divided
85  * @alt_parent:	alternate parent clock to use when switching the speed
230 	 * the alternate parent, then it should be ensured that at no point  in exynos_cpuclk_pre_rate_change()
255 	/* select sclk_mpll as the alternate parent */  in exynos_cpuclk_pre_rate_change()
260 	/* alternate parent is active now. set the dividers */  in exynos_cpuclk_pre_rate_change()
296 	/* select mout_apll as the alternate parent */  in exynos_cpuclk_post_rate_change()
351 	 * the alternate parent, then it should be ensured that at no point  in exynos5433_cpuclk_pre_rate_change()
368 	/* select the alternate parent */  in exynos5433_cpuclk_pre_rate_change()
373 	/* alternate parent is active now. set the dividers */  in exynos5433_cpuclk_pre_rate_change()
396 	/* select apll as the alternate parent */  in exynos5433_cpuclk_post_rate_change()
427  * Set alternate parent rate to "rate" value or less.
433  * instead to adjust alternate parent speed.
436  * would set overly pessimistic rate values to alternate parent.
503 	 * the alternate parent, then it should be ensured that at no point  in exynos850_cpuclk_pre_rate_change()
519 	/* Select the alternate parent */  in exynos850_cpuclk_pre_rate_change()
524 	/* Alternate parent is active now. Set the dividers */  in exynos850_cpuclk_pre_rate_change()