Lines Matching +full:15 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
33 RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM
34 RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15),
42 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9),
45 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15),
53 RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15),
63 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9),
72 RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15),
95 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1),
96 RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2),
97 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5),
98 RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6),
99 RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7),
110 RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9),
116 RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15),
128 RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9),
145 RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9),
153 RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9),
155 RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15),
163 RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9),
169 RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15),
172 RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0),
173 RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1),
174 RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2),
175 RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3),
176 RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4),
177 RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6),
178 RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7),
179 RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9),
180 RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10),
181 RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12),
182 RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13),
183 RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15),
195 RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9),
201 RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15),
213 RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9),
218 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15),
228 RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9),
247 RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9),
253 RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15),
267 RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15),
290 RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9),
296 RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15),
310 RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15),
346 RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9),
361 RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9),
371 RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9),
380 RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9),
386 RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15),
394 RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15),
401 RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9),
412 RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9),
418 RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15),
428 RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9),
449 RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15),
462 RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9),
468 RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15),
480 RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9),
517 RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9),
525 RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9),
534 RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9),
537 RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15),
549 RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9),
556 RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9),
561 RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15),
566 RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9),
582 RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
602 RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9),
613 RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15),
625 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15),
633 RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15),
646 RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9),
651 RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15),
685 RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9),
699 RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9),
705 RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM
717 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM
752 RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9),
784 RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15),
791 RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15),
802 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9),
817 RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15),
824 RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9),
830 RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15),
839 RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15),