Lines Matching refs:RK3576_PMU1CRU_RESET_OFFSET
21 #define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) macro
571 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0),
572 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1),
573 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
574 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3),
575 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4),
576 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5),
577 RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6),
578 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
579 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8),
580 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
581 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10),
582 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
583 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12),
584 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15),
587 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0),
588 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1),
589 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
590 RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3),
591 RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4),
592 RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5),
593 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6),
594 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
595 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8),
596 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
597 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10),
598 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
599 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13),
602 RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
603 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
604 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
607 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
608 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10),
609 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
610 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12),
611 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13),
614 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1),
615 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3),
616 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4),
617 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5),
618 RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6),
619 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7),
620 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
621 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10),
622 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11),
623 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12),
626 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1),
627 RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2),
628 RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5),
629 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6),
630 RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13),
631 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15),
634 RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0),
635 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1),
638 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4),
639 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5),
640 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6),
641 RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7),