Lines Matching +full:2 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
33 RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
34 RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
37 RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2),
40 RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
47 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
65 RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
66 RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
67 RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
68 RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
69 RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
70 RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
71 RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
72 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
73 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
74 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
75 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
84 RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
93 RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2),
100 RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
111 RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
117 RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
128 RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
133 RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
138 RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2),
141 RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
151 RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2),
158 RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
168 RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
178 RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2),
185 RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
195 RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2),
200 RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
212 RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
218 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2),
231 RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2),
235 RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
244 RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2),
250 RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
255 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2),
263 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2),
274 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
280 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2),
286 RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
296 RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2),
307 RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2),
312 RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
320 RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
333 RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
338 RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2),
346 RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2),
356 RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
361 RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2),
376 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
390 RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2),
405 RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2),
416 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2),
443 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2),
454 RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
460 RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2),
466 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
476 RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
484 RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
492 RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2),
497 RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
506 RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2),
511 RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
520 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
531 RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
541 RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2),
547 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2),
568 RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
573 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
580 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
589 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
596 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
602 RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
603 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
604 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
607 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
620 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
627 RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2),