Lines Matching +full:15 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
47 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
52 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15),
65 RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
66 RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
67 RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
68 RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
69 RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
70 RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
71 RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
72 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
73 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
74 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
75 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
84 RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
88 RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15),
100 RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
106 RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15),
117 RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
123 RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15),
133 RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
135 RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15),
138 RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2),
139 RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5),
140 RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8),
141 RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
142 RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10),
143 RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11),
144 RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13),
145 RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14),
146 RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15),
158 RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
168 RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
173 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15),
185 RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
190 RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15),
200 RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
212 RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
226 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15),
235 RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
240 RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15),
250 RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
274 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
286 RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
291 RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15),
312 RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
320 RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
322 RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15),
333 RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
356 RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
376 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
385 RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15),
400 RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15),
454 RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
466 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
476 RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
484 RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
488 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15),
497 RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
511 RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
520 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
523 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15),
531 RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
568 RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
580 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
584 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15),
596 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
607 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
620 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
631 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15),