Lines Matching +full:1 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
26 RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
27 RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5),
28 RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6),
29 RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
30 RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14),
34 RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
47 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
56 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1),
65 RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
66 RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
67 RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
68 RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
69 RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
70 RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
71 RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
72 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
73 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
74 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
75 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
84 RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
92 RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1),
100 RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
110 RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1),
117 RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
127 RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1),
133 RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
141 RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
150 RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1),
158 RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
168 RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
177 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1),
185 RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
194 RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1),
200 RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
207 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1),
212 RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
217 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1),
230 RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1),
235 RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
243 RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1),
250 RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
254 RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1),
262 RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1),
271 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1),
274 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
285 RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1),
286 RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
295 RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1),
312 RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
318 RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1),
320 RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
333 RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
337 RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1),
356 RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
376 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
389 RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1),
404 RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1),
433 RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1),
442 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1),
454 RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
459 RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1),
466 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
476 RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
484 RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
497 RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
511 RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
520 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
531 RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
537 RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1),
540 RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1),
546 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1),
553 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1),
561 RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5),
562 RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8),
568 RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
572 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1),
580 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
587 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0),
588 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1),
589 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
590 RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3),
591 RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4),
592 RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5),
593 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6),
594 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
595 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8),
596 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
597 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10),
598 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
599 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13),
603 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
607 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
614 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1),
620 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
626 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1),
635 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1),