Lines Matching +full:11 +full:- +full:7
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
9 #include <dt-bindings/reset/rockchip,rk3506-cru.h>
17 /* CRU-->SOFTRST_CON00 */
28 /* CRU-->SOFTRST_CON02 */
33 /* CRU-->SOFTRST_CON03 */
38 RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
42 /* CRU-->SOFTRST_CON04 */
46 RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
49 RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
53 /* CRU-->SOFTRST_CON05 */
58 RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7),
62 RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11),
65 /* CRU-->SOFTRST_CON06 */
73 RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7),
77 RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11),
83 /* CRU-->SOFTRST_CON07 */
84 RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0),
85 RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1),
86 RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2),
87 RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3),
88 RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4),
89 RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5),
90 RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7),
91 RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8),
92 RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10),
93 RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11),
94 RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12),
95 RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
96 RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14),
98 /* CRU-->SOFTRST_CON08 */
102 /* CRU-->SOFTRST_CON09 */
106 /* CRU-->SOFTRST_CON10 */
113 /* CRU-->SOFTRST_CON11 */
114 RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2),
115 RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4),
116 RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5),
117 RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6),
118 RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7),
119 RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8),
120 RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9),
121 RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10),
122 RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11),
123 RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12),
124 RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
125 RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14),
126 RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15),
128 /* CRU-->SOFTRST_CON12 */
136 RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11),
142 /* CRU-->SOFTRST_CON13 */
150 RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7),
154 RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11),
160 /* CRU-->SOFTRST_CON14 */
166 RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7),
169 /* CRU-->SOFTRST_CON17 */
171 RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7),
175 RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11),
178 /* CRU-->SOFTRST_CON18 */
182 RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7),
184 RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11),
190 /* CRU-->SOFTRST_CON19 */
198 RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7),
201 /* CRU-->SOFTRST_CON21 */
205 RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7),
209 RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11),
215 /* CRU-->SOFTRST_CON22 */