Lines Matching +full:0 +full:x584
29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
39 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
40 #define BOOST_RECOVERY_MASK 0x1
42 #define BOOST_SW_CTRL_MASK 0x1
44 #define BOOST_LOW_FREQ_EN_MASK 0x1
48 #define PX30_PLL_CON(x) ((x) * 0x4)
49 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
50 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
51 #define PX30_GLB_SRST_FST 0xb8
52 #define PX30_GLB_SRST_SND 0xbc
53 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
54 #define PX30_MODE_CON 0xa0
55 #define PX30_MISC_CON 0xa4
56 #define PX30_SDMMC_CON0 0x380
57 #define PX30_SDMMC_CON1 0x384
58 #define PX30_SDIO_CON0 0x388
59 #define PX30_SDIO_CON1 0x38c
60 #define PX30_EMMC_CON0 0x390
61 #define PX30_EMMC_CON1 0x394
63 #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
64 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
65 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
66 #define PX30_PMU_MODE 0x0020
68 #define RV1108_PLL_CON(x) ((x) * 0x4)
69 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
70 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
71 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
72 #define RV1108_GLB_SRST_FST 0x1c0
73 #define RV1108_GLB_SRST_SND 0x1c4
74 #define RV1108_MISC_CON 0x1cc
75 #define RV1108_SDMMC_CON0 0x1d8
76 #define RV1108_SDMMC_CON1 0x1dc
77 #define RV1108_SDIO_CON0 0x1e0
78 #define RV1108_SDIO_CON1 0x1e4
79 #define RV1108_EMMC_CON0 0x1e8
80 #define RV1108_EMMC_CON1 0x1ec
82 #define RV1126_PMU_MODE 0x0
83 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
84 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
85 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
86 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
87 #define RV1126_PLL_CON(x) ((x) * 0x4)
88 #define RV1126_MODE_CON 0x90
89 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
90 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
91 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
92 #define RV1126_GLB_SRST_FST 0x408
93 #define RV1126_GLB_SRST_SND 0x40c
94 #define RV1126_SDMMC_CON0 0x440
95 #define RV1126_SDMMC_CON1 0x444
96 #define RV1126_SDIO_CON0 0x448
97 #define RV1126_SDIO_CON1 0x44c
98 #define RV1126_EMMC_CON0 0x450
99 #define RV1126_EMMC_CON1 0x454
101 #define RK2928_PLL_CON(x) ((x) * 0x4)
102 #define RK2928_MODE_CON 0x40
103 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
104 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
105 #define RK2928_GLB_SRST_FST 0x100
106 #define RK2928_GLB_SRST_SND 0x104
107 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
108 #define RK2928_MISC_CON 0x134
110 #define RK3036_SDMMC_CON0 0x144
111 #define RK3036_SDMMC_CON1 0x148
112 #define RK3036_SDIO_CON0 0x14c
113 #define RK3036_SDIO_CON1 0x150
114 #define RK3036_EMMC_CON0 0x154
115 #define RK3036_EMMC_CON1 0x158
117 #define RK3228_GLB_SRST_FST 0x1f0
118 #define RK3228_GLB_SRST_SND 0x1f4
119 #define RK3228_SDMMC_CON0 0x1c0
120 #define RK3228_SDMMC_CON1 0x1c4
121 #define RK3228_SDIO_CON0 0x1c8
122 #define RK3228_SDIO_CON1 0x1cc
123 #define RK3228_EMMC_CON0 0x1d8
124 #define RK3228_EMMC_CON1 0x1dc
127 #define RK3288_MODE_CON 0x50
128 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
129 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
130 #define RK3288_GLB_SRST_FST 0x1b0
131 #define RK3288_GLB_SRST_SND 0x1b4
132 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
133 #define RK3288_MISC_CON 0x1e8
134 #define RK3288_SDMMC_CON0 0x200
135 #define RK3288_SDMMC_CON1 0x204
136 #define RK3288_SDIO0_CON0 0x208
137 #define RK3288_SDIO0_CON1 0x20c
138 #define RK3288_SDIO1_CON0 0x210
139 #define RK3288_SDIO1_CON1 0x214
140 #define RK3288_EMMC_CON0 0x218
141 #define RK3288_EMMC_CON1 0x21c
144 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
145 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
146 #define RK3308_GLB_SRST_FST 0xb8
147 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
148 #define RK3308_MODE_CON 0xa0
149 #define RK3308_SDMMC_CON0 0x480
150 #define RK3308_SDMMC_CON1 0x484
151 #define RK3308_SDIO_CON0 0x488
152 #define RK3308_SDIO_CON1 0x48c
153 #define RK3308_EMMC_CON0 0x490
154 #define RK3308_EMMC_CON1 0x494
157 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
158 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
159 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
160 #define RK3328_GLB_SRST_FST 0x9c
161 #define RK3328_GLB_SRST_SND 0x98
162 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
163 #define RK3328_MODE_CON 0x80
164 #define RK3328_MISC_CON 0x84
165 #define RK3328_SDMMC_CON0 0x380
166 #define RK3328_SDMMC_CON1 0x384
167 #define RK3328_SDIO_CON0 0x388
168 #define RK3328_SDIO_CON1 0x38c
169 #define RK3328_EMMC_CON0 0x390
170 #define RK3328_EMMC_CON1 0x394
171 #define RK3328_SDMMC_EXT_CON0 0x398
172 #define RK3328_SDMMC_EXT_CON1 0x39C
175 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
176 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
177 #define RK3368_GLB_SRST_FST 0x280
178 #define RK3368_GLB_SRST_SND 0x284
179 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
180 #define RK3368_MISC_CON 0x380
181 #define RK3368_SDMMC_CON0 0x400
182 #define RK3368_SDMMC_CON1 0x404
183 #define RK3368_SDIO0_CON0 0x408
184 #define RK3368_SDIO0_CON1 0x40c
185 #define RK3368_SDIO1_CON0 0x410
186 #define RK3368_SDIO1_CON1 0x414
187 #define RK3368_EMMC_CON0 0x418
188 #define RK3368_EMMC_CON1 0x41c
191 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
192 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
193 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
194 #define RK3399_GLB_SRST_FST 0x500
195 #define RK3399_GLB_SRST_SND 0x504
196 #define RK3399_GLB_CNT_TH 0x508
197 #define RK3399_MISC_CON 0x50c
198 #define RK3399_RST_CON 0x510
199 #define RK3399_RST_ST 0x514
200 #define RK3399_SDMMC_CON0 0x580
201 #define RK3399_SDMMC_CON1 0x584
202 #define RK3399_SDIO_CON0 0x588
203 #define RK3399_SDIO_CON1 0x58c
206 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
207 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
208 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
211 #define RK3568_MODE_CON0 0xc0
212 #define RK3568_MISC_CON0 0xc4
213 #define RK3568_MISC_CON1 0xc8
214 #define RK3568_MISC_CON2 0xcc
215 #define RK3568_GLB_CNT_TH 0xd0
216 #define RK3568_GLB_SRST_FST 0xd4
217 #define RK3568_GLB_SRST_SND 0xd8
218 #define RK3568_GLB_RST_CON 0xdc
219 #define RK3568_GLB_RST_ST 0xe0
220 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
221 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
222 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
223 #define RK3568_SDMMC0_CON0 0x580
224 #define RK3568_SDMMC0_CON1 0x584
225 #define RK3568_SDMMC1_CON0 0x588
226 #define RK3568_SDMMC1_CON1 0x58c
227 #define RK3568_SDMMC2_CON0 0x590
228 #define RK3568_SDMMC2_CON1 0x594
229 #define RK3568_EMMC_CON0 0x598
230 #define RK3568_EMMC_CON1 0x59c
233 #define RK3568_PMU_MODE_CON0 0x80
234 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
235 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
236 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
238 #define RK3576_PHP_CRU_BASE 0x8000
239 #define RK3576_SECURE_NS_CRU_BASE 0x10000
240 #define RK3576_PMU_CRU_BASE 0x20000
241 #define RK3576_BIGCORE_CRU_BASE 0x38000
242 #define RK3576_LITCORE_CRU_BASE 0x40000
243 #define RK3576_CCI_CRU_BASE 0x48000
246 #define RK3576_MODE_CON0 0x280
247 #define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
248 #define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
249 #define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
250 #define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
251 #define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
252 #define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
253 #define RK3576_GLB_CNT_TH 0xc00
254 #define RK3576_GLB_SRST_FST 0xc08
255 #define RK3576_GLB_SRST_SND 0xc0c
256 #define RK3576_GLB_RST_CON 0xc10
257 #define RK3576_GLB_RST_ST 0xc04
258 #define RK3576_SDIO_CON0 0xC24
259 #define RK3576_SDIO_CON1 0xC28
260 #define RK3576_SDMMC_CON0 0xC30
261 #define RK3576_SDMMC_CON1 0xC34
263 #define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
264 #define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
265 #define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
267 #define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
268 #define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
269 #define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
270 #define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
272 #define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300)
273 #define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800)
274 #define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00)
276 #define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
277 #define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
278 #define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
280 #define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
281 #define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
282 #define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
283 #define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
284 #define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
285 #define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
286 #define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
287 #define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
288 #define RK3576_NON_SECURE_GATING_CON00 0xc48
290 #define RK3588_PHP_CRU_BASE 0x8000
291 #define RK3588_PMU_CRU_BASE 0x30000
292 #define RK3588_BIGCORE0_CRU_BASE 0x50000
293 #define RK3588_BIGCORE1_CRU_BASE 0x52000
294 #define RK3588_DSU_CRU_BASE 0x58000
297 #define RK3588_MODE_CON0 0x280
298 #define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280)
299 #define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280)
300 #define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280)
301 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
302 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
303 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
304 #define RK3588_GLB_CNT_TH 0xc00
305 #define RK3588_GLB_SRST_FST 0xc08
306 #define RK3588_GLB_SRST_SND 0xc0c
307 #define RK3588_GLB_RST_CON 0xc10
308 #define RK3588_GLB_RST_ST 0xc04
309 #define RK3588_SDIO_CON0 0xC24
310 #define RK3588_SDIO_CON1 0xC28
311 #define RK3588_SDMMC_CON0 0xC30
312 #define RK3588_SDMMC_CON1 0xC34
314 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
315 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
317 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
318 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
319 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
320 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
322 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
323 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
324 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
325 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
326 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
327 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
328 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
329 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
330 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
331 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
332 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
333 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
463 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
542 #define ROCKCHIP_DDRCLK_SIP BIT(0)
552 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
1023 FACTOR(_id, cname, pname, 0, 1, 1)
1047 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)