Lines Matching refs:DFLAGS
212 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
273 RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
282 RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
295 RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
308 RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
313 RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
321 RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
328 RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
334 RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
351 RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
365 RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
403 RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
412 RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
420 RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
425 RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
430 RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
446 RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
460 RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
471 RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
482 RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
494 DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
505 DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
516 RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
521 RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
526 RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
531 RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
537 RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
545 RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
572 RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
598 RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
604 RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
613 RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
620 RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
630 RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
636 RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
646 RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
665 RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
680 RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
696 RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
702 RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
719 RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
727 RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
730 RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
733 RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
740 RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
747 RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
762 RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
770 RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
773 RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
782 DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
792 RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
803 RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
808 RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
815 RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
830 RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
840 RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
848 RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
884 RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
908 RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
1009 RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
1016 RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
1019 RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,