Lines Matching +full:pll +full:-
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
51 struct rockchip_clk_pll *pll, unsigned long rate)
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
56 for (i = 0; i < pll->rate_count; i++) {
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
72 for (i = 0; i < pll->rate_count; i++) {
78 return rate_table[i - 1].rate;
82 * Wait for the pll to reach the locked state.
86 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
88 struct regmap *grf = pll->ctx->grf;
92 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
93 val & BIT(pll->lock_shift), 0, 1000);
95 pr_err("%s: timeout waiting for pll to lock\n", __func__);
101 * PLL used in RK3036
120 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
129 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
134 pr_err("%s: timeout waiting for pll to lock\n", __func__);
139 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
144 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
150 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
151 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
155 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
158 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
159 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
166 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
170 rockchip_rk3036_pll_get_params(pll, &cur);
189 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
192 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
193 struct clk_mux *pll_mux = &pll->pll_mux;
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
202 rate->postdiv2, rate->dsmpd, rate->frac);
204 rockchip_rk3036_pll_get_params(pll, &cur);
207 if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
208 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
210 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
215 /* update pll values */
216 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
218 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
220 pll->reg_base + RK3036_PLLCON(0));
222 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
224 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
226 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
228 pll->reg_base + RK3036_PLLCON(1));
231 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
233 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
234 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
236 /* wait for the pll to lock */
237 ret = rockchip_rk3036_pll_wait_lock(pll);
239 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
241 rockchip_rk3036_pll_set_params(pll, &cur);
245 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
253 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
257 __func__, __clk_get_name(hw->clk), drate, prate);
260 rate = rockchip_get_pll_settings(pll, drate);
262 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
263 drate, __clk_get_name(hw->clk));
264 return -EINVAL;
267 return rockchip_rk3036_pll_set_params(pll, rate);
272 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
275 pll->reg_base + RK3036_PLLCON(1));
276 rockchip_rk3036_pll_wait_lock(pll);
283 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
287 pll->reg_base + RK3036_PLLCON(1));
292 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
293 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
300 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
305 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
309 rate = rockchip_get_pll_settings(pll, drate);
315 rockchip_rk3036_pll_get_params(pll, &cur);
317 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
319 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
322 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
323 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
324 rate->dsmpd, rate->frac);
326 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
327 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
328 rate->dsmpd != cur.dsmpd ||
329 (!cur.dsmpd && (rate->frac != cur.frac))) {
330 struct clk *parent = clk_get_parent(hw->clk);
334 __func__, __clk_get_name(hw->clk));
338 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
339 __func__, __clk_get_name(hw->clk));
340 rockchip_rk3036_pll_set_params(pll, rate);
364 * PLL used in RK3066, RK3188 and RK3288
382 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
387 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
388 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
390 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
393 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
394 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
397 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
398 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
405 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
410 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
412 pr_debug("%s: pll %s is bypassed\n", __func__,
417 rockchip_rk3066_pll_get_params(pll, &cur);
426 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
429 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
430 struct clk_mux *pll_mux = &pll->pll_mux;
437 __func__, rate->rate, rate->nr, rate->no, rate->nf);
439 rockchip_rk3066_pll_get_params(pll, &cur);
442 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
444 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
450 pll->reg_base + RK3066_PLLCON(3));
452 /* update pll values */
453 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
455 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
457 pll->reg_base + RK3066_PLLCON(0));
459 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
461 pll->reg_base + RK3066_PLLCON(1));
462 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
464 pll->reg_base + RK3066_PLLCON(2));
468 pll->reg_base + RK3066_PLLCON(3));
469 udelay(RK3066_PLL_RESET_DELAY(rate->nr));
471 /* wait for the pll to lock */
472 ret = rockchip_pll_wait_lock(pll);
474 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
476 rockchip_rk3066_pll_set_params(pll, &cur);
480 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
488 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
495 rate = rockchip_get_pll_settings(pll, drate);
497 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
499 return -EINVAL;
502 return rockchip_rk3066_pll_set_params(pll, rate);
507 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
510 pll->reg_base + RK3066_PLLCON(3));
511 rockchip_pll_wait_lock(pll);
518 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
522 pll->reg_base + RK3066_PLLCON(3));
527 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
528 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
535 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
540 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
544 rate = rockchip_get_pll_settings(pll, drate);
550 rockchip_rk3066_pll_get_params(pll, &cur);
552 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
553 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
554 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
555 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
556 || rate->nb != cur.nb) {
557 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
559 rockchip_rk3066_pll_set_params(pll, rate);
583 * PLL used in RK3399
602 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
611 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
616 pr_err("%s: timeout waiting for pll to lock\n", __func__);
621 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
626 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
627 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
630 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
631 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
633 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
635 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
638 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
639 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
642 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
643 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
650 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
654 rockchip_rk3399_pll_get_params(pll, &cur);
673 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
676 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
677 struct clk_mux *pll_mux = &pll->pll_mux;
685 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
686 rate->postdiv2, rate->dsmpd, rate->frac);
688 rockchip_rk3399_pll_get_params(pll, &cur);
691 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
693 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
697 /* update pll values */
698 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
700 pll->reg_base + RK3399_PLLCON(0));
702 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
704 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
706 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
708 pll->reg_base + RK3399_PLLCON(1));
711 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
713 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
714 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
716 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
718 pll->reg_base + RK3399_PLLCON(3));
720 /* wait for the pll to lock */
721 ret = rockchip_rk3399_pll_wait_lock(pll);
723 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
725 rockchip_rk3399_pll_set_params(pll, &cur);
729 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
737 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
741 __func__, __clk_get_name(hw->clk), drate, prate);
744 rate = rockchip_get_pll_settings(pll, drate);
746 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
747 drate, __clk_get_name(hw->clk));
748 return -EINVAL;
751 return rockchip_rk3399_pll_set_params(pll, rate);
756 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
759 pll->reg_base + RK3399_PLLCON(3));
760 rockchip_rk3399_pll_wait_lock(pll);
767 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
771 pll->reg_base + RK3399_PLLCON(3));
776 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
777 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
784 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
789 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
793 rate = rockchip_get_pll_settings(pll, drate);
799 rockchip_rk3399_pll_get_params(pll, &cur);
801 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
803 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
806 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
807 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
808 rate->dsmpd, rate->frac);
810 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
811 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
812 rate->dsmpd != cur.dsmpd ||
813 (!cur.dsmpd && (rate->frac != cur.frac))) {
814 struct clk *parent = clk_get_parent(hw->clk);
818 __func__, __clk_get_name(hw->clk));
822 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
823 __func__, __clk_get_name(hw->clk));
824 rockchip_rk3399_pll_set_params(pll, rate);
848 * PLL used in RK3588
863 static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
872 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6),
877 pr_err("%s: timeout waiting for pll to lock\n", __func__);
882 static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll,
887 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0));
888 rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK);
890 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1));
891 rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK);
892 rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK);
894 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2));
895 rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
900 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
904 rockchip_rk3588_pll_get_params(pll, &cur);
919 if (pll->type == pll_rk3588_ddr)
925 static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
928 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
929 struct clk_mux *pll_mux = &pll->pll_mux;
936 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
938 rockchip_rk3588_pll_get_params(pll, &cur);
941 if (pll->type == pll_rk3588) {
942 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
944 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
949 /* set pll power down */
952 pll->reg_base + RK3399_PLLCON(1));
954 /* update pll values */
955 writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT),
956 pll->reg_base + RK3399_PLLCON(0));
958 writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) |
959 HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT),
960 pll->reg_base + RK3399_PLLCON(1));
962 writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),
963 pll->reg_base + RK3399_PLLCON(2));
965 /* set pll power up */
967 pll->reg_base + RK3588_PLLCON(1));
969 /* wait for the pll to lock */
970 ret = rockchip_rk3588_pll_wait_lock(pll);
972 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
974 rockchip_rk3588_pll_set_params(pll, &cur);
977 if ((pll->type == pll_rk3588) && rate_change_remuxed)
978 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
986 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
990 __func__, __clk_get_name(hw->clk), drate, prate);
993 rate = rockchip_get_pll_settings(pll, drate);
995 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
996 drate, __clk_get_name(hw->clk));
997 return -EINVAL;
1000 return rockchip_rk3588_pll_set_params(pll, rate);
1005 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1008 pll->reg_base + RK3588_PLLCON(1));
1009 rockchip_rk3588_pll_wait_lock(pll);
1016 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1019 pll->reg_base + RK3588_PLLCON(1));
1024 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1025 u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1));
1047 * Common registering of pll clocks
1060 struct rockchip_clk_pll *pll;
1068 return ERR_PTR(-EINVAL);
1071 /* name the actual pll */
1074 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1075 if (!pll)
1076 return ERR_PTR(-ENOMEM);
1078 /* create the mux on top of the real pll */
1079 pll->pll_mux_ops = &clk_mux_ops;
1080 pll_mux = &pll->pll_mux;
1081 pll_mux->reg = ctx->reg_base + mode_offset;
1082 pll_mux->shift = mode_shift;
1084 pll_mux->mask = PLL_RK3328_MODE_MASK;
1086 pll_mux->mask = PLL_MODE_MASK;
1087 pll_mux->flags = 0;
1088 pll_mux->lock = &ctx->lock;
1089 pll_mux->hw.init = &init;
1096 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
1098 /* the actual muxing is xin24m, pll-output, xin32k */
1105 init.ops = pll->pll_mux_ops;
1112 mux_clk = clk_register(NULL, &pll_mux->hw);
1116 /* now create the actual pll */
1132 pll->rate_count = len;
1133 pll->rate_table = kmemdup_array(rate_table,
1134 pll->rate_count,
1135 sizeof(*pll->rate_table),
1137 WARN(!pll->rate_table,
1145 if (!pll->rate_table)
1151 if (!pll->rate_table || IS_ERR(ctx->grf))
1157 if (!pll->rate_table)
1165 if (!pll->rate_table)
1172 pr_warn("%s: Unknown pll type for pll clk %s\n",
1176 pll->hw.init = &init;
1177 pll->type = pll_type;
1178 pll->reg_base = ctx->reg_base + con_offset;
1179 pll->lock_offset = grf_lock_offset;
1180 pll->lock_shift = lock_shift;
1181 pll->flags = clk_pll_flags;
1182 pll->lock = &ctx->lock;
1183 pll->ctx = ctx;
1185 pll_clk = clk_register(NULL, &pll->hw);
1187 pr_err("%s: failed to register pll clock %s : %ld\n",
1195 kfree(pll->rate_table);
1199 kfree(pll);