1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
40  * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
57 	raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);  in rockchip_mmc_get_phase()
81 	u32 delay;  in rockchip_mmc_set_phase()  local
97 		return -EINVAL;  in rockchip_mmc_set_phase()
104 	 * Due to the inexact nature of the "fine" delay, we might  in rockchip_mmc_set_phase()
105 	 * actually go non-monotonic.  We don't go _too_ monotonic  in rockchip_mmc_set_phase()
112 	 * On one extreme (if delay is actually 44ps):  in rockchip_mmc_set_phase()
114 	 * The other (if delay is actually 77ps):  in rockchip_mmc_set_phase()
117 	 * It's possible we might make a delay that is up to 25  in rockchip_mmc_set_phase()
123 	 * Convert to delay; do a little extra work to make sure we  in rockchip_mmc_set_phase()
124 	 * don't overflow 32-bit / 64-bit numbers.  in rockchip_mmc_set_phase()
126 	delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */  in rockchip_mmc_set_phase()
127 	delay *= remainder;  in rockchip_mmc_set_phase()
128 	delay = DIV_ROUND_CLOSEST(delay,  in rockchip_mmc_set_phase()
132 	delay_num = (u8) min_t(u32, delay, 255);  in rockchip_mmc_set_phase()
137 	writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),  in rockchip_mmc_set_phase()
138 	       mmc_clock->reg);  in rockchip_mmc_set_phase()
140 	pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",  in rockchip_mmc_set_phase()
142 		mmc_clock->reg, raw_value>>(mmc_clock->shift),  in rockchip_mmc_set_phase()
174 	 * set the max-frequency to match the boards' ability but we can't go  in rockchip_mmc_clk_rate_notify()
177 	if (ndata->old_rate <= ndata->new_rate)  in rockchip_mmc_clk_rate_notify()
181 		mmc_clock->cached_phase =  in rockchip_mmc_clk_rate_notify()
182 			rockchip_mmc_get_phase(&mmc_clock->hw);  in rockchip_mmc_clk_rate_notify()
183 	else if (mmc_clock->cached_phase != -EINVAL &&  in rockchip_mmc_clk_rate_notify()
185 		rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);  in rockchip_mmc_clk_rate_notify()
194 	struct clk_init_data init;  in rockchip_clk_register_mmc()  local
201 		return ERR_PTR(-ENOMEM);  in rockchip_clk_register_mmc()
203 	init.name = name;  in rockchip_clk_register_mmc()
204 	init.flags = 0;  in rockchip_clk_register_mmc()
205 	init.num_parents = num_parents;  in rockchip_clk_register_mmc()
206 	init.parent_names = parent_names;  in rockchip_clk_register_mmc()
207 	init.ops = &rockchip_mmc_clk_ops;  in rockchip_clk_register_mmc()
209 	mmc_clock->hw.init = &init;  in rockchip_clk_register_mmc()
210 	mmc_clock->reg = reg;  in rockchip_clk_register_mmc()
211 	mmc_clock->shift = shift;  in rockchip_clk_register_mmc()
213 	clk = clk_register(NULL, &mmc_clock->hw);  in rockchip_clk_register_mmc()
219 	mmc_clock->clk_rate_change_nb.notifier_call =  in rockchip_clk_register_mmc()
221 	ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);  in rockchip_clk_register_mmc()