Lines Matching +full:default +full:- +full:sample +full:- +full:phase

1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
43 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
56 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
60 if (mmc_clock->grf) in rockchip_mmc_get_phase()
61 regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value); in rockchip_mmc_get_phase()
63 raw_value = readl(mmc_clock->reg); in rockchip_mmc_get_phase()
65 raw_value >>= mmc_clock->shift; in rockchip_mmc_get_phase()
93 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
105 return -EINVAL; in rockchip_mmc_set_phase()
113 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
132 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase()
145 raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift); in rockchip_mmc_set_phase()
147 if (mmc_clock->grf) in rockchip_mmc_set_phase()
148 regmap_write(mmc_clock->grf, mmc_clock->grf_reg, raw_value); in rockchip_mmc_set_phase()
150 writel(raw_value, mmc_clock->reg); in rockchip_mmc_set_phase()
152 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", in rockchip_mmc_set_phase()
154 mmc_clock->reg, raw_value>>(mmc_clock->shift), in rockchip_mmc_set_phase()
176 * rockchip_mmc_clk is mostly used by mmc controllers to sample in rockchip_mmc_clk_rate_notify()
177 * the intput data, which expects the fixed phase after the tuning in rockchip_mmc_clk_rate_notify()
178 * process. However if the clock rate is changed, the phase is stale in rockchip_mmc_clk_rate_notify()
179 * and may break the data sampling. So here we try to restore the phase in rockchip_mmc_clk_rate_notify()
184 * since we only set the default sample phase and drive phase later on. in rockchip_mmc_clk_rate_notify()
186 * set the max-frequency to match the boards' ability but we can't go in rockchip_mmc_clk_rate_notify()
189 if (ndata->old_rate <= ndata->new_rate) in rockchip_mmc_clk_rate_notify()
193 mmc_clock->cached_phase = in rockchip_mmc_clk_rate_notify()
194 rockchip_mmc_get_phase(&mmc_clock->hw); in rockchip_mmc_clk_rate_notify()
195 else if (mmc_clock->cached_phase != -EINVAL && in rockchip_mmc_clk_rate_notify()
197 rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase); in rockchip_mmc_clk_rate_notify()
215 return ERR_PTR(-ENOMEM); in rockchip_clk_register_mmc()
223 mmc_clock->hw.init = &init; in rockchip_clk_register_mmc()
224 mmc_clock->reg = reg; in rockchip_clk_register_mmc()
225 mmc_clock->grf = grf; in rockchip_clk_register_mmc()
226 mmc_clock->grf_reg = grf_reg; in rockchip_clk_register_mmc()
227 mmc_clock->shift = shift; in rockchip_clk_register_mmc()
229 clk = clk_register(NULL, &mmc_clock->hw); in rockchip_clk_register_mmc()
235 mmc_clock->clk_rate_change_nb.notifier_call = in rockchip_clk_register_mmc()
237 ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb); in rockchip_clk_register_mmc()