32 	struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);  in rockchip_ddrclk_sip_set_rate()  local
36 	spin_lock_irqsave(ddrclk->lock, flags);  in rockchip_ddrclk_sip_set_rate()
40 	spin_unlock_irqrestore(ddrclk->lock, flags);  in rockchip_ddrclk_sip_set_rate()
73 	struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);  in rockchip_ddrclk_get_parent()  local
76 	val = readl(ddrclk->reg_base +  in rockchip_ddrclk_get_parent()
77 			ddrclk->mux_offset) >> ddrclk->mux_shift;  in rockchip_ddrclk_get_parent()
78 	val &= GENMASK(ddrclk->mux_width - 1, 0);  in rockchip_ddrclk_get_parent()
98 	struct rockchip_ddrclk *ddrclk;  in rockchip_clk_register_ddrclk()  local
102 	ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);  in rockchip_clk_register_ddrclk()
103 	if (!ddrclk)  in rockchip_clk_register_ddrclk()
119 		kfree(ddrclk);  in rockchip_clk_register_ddrclk()
123 	ddrclk->reg_base = reg_base;  in rockchip_clk_register_ddrclk()
124 	ddrclk->lock = lock;  in rockchip_clk_register_ddrclk()
125 	ddrclk->hw.init = &init;  in rockchip_clk_register_ddrclk()
126 	ddrclk->mux_offset = mux_offset;  in rockchip_clk_register_ddrclk()
127 	ddrclk->mux_shift = mux_shift;  in rockchip_clk_register_ddrclk()
128 	ddrclk->mux_width = mux_width;  in rockchip_clk_register_ddrclk()
129 	ddrclk->div_shift = div_shift;  in rockchip_clk_register_ddrclk()
130 	ddrclk->div_width = div_width;  in rockchip_clk_register_ddrclk()
131 	ddrclk->ddr_flag = ddr_flag;  in rockchip_clk_register_ddrclk()
133 	clk = clk_register(NULL, &ddrclk->hw);  in rockchip_clk_register_ddrclk()
135 		kfree(ddrclk);  in rockchip_clk_register_ddrclk()