Lines Matching +full:r9a09g057 +full:- +full:cpg
1 // SPDX-License-Identifier: GPL-2.0
7 * Based on rzg2l-cpg.c
16 #include <linux/clk-provider.h>
27 #include <linux/reset-controller.h>
30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 #include "rzv2h-cpg.h"
46 #define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
69 * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
71 * @dev: CPG device
72 * @base: CPG register block base address
78 * @num_resets: Number of Module Resets in info->resets[]
112 * struct mod_clock - Module clock
114 * @priv: CPG private data
116 * @hw: handle between common and hardware-specific interfaces
137 * struct ddiv_clk - DDIV clock
139 * @priv: CPG private data
154 struct rzv2h_cpg_priv *priv = pll_clk->priv; in rzv2h_cpg_pll_clk_is_enabled()
155 u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset)); in rzv2h_cpg_pll_clk_is_enabled()
165 struct rzv2h_cpg_priv *priv = pll_clk->priv; in rzv2h_cpg_pll_clk_enable()
166 struct pll pll = pll_clk->pll; in rzv2h_cpg_pll_clk_enable()
179 priv->base + stby_offset); in rzv2h_cpg_pll_clk_enable()
189 ret = readl_poll_timeout_atomic(priv->base + mon_offset, val, in rzv2h_cpg_pll_clk_enable()
193 dev_err(priv->dev, "Failed to enable PLL 0x%x/%pC\n", in rzv2h_cpg_pll_clk_enable()
194 stby_offset, hw->clk); in rzv2h_cpg_pll_clk_enable()
203 struct rzv2h_cpg_priv *priv = pll_clk->priv; in rzv2h_cpg_pll_clk_recalc_rate()
204 struct pll pll = pll_clk->pll; in rzv2h_cpg_pll_clk_recalc_rate()
211 clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset)); in rzv2h_cpg_pll_clk_recalc_rate()
212 clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset)); in rzv2h_cpg_pll_clk_recalc_rate()
231 void __iomem *base = priv->base; in rzv2h_cpg_pll_clk_register()
232 struct device *dev = priv->dev; in rzv2h_cpg_pll_clk_register()
239 parent = priv->clks[core->parent]; in rzv2h_cpg_pll_clk_register()
245 return ERR_PTR(-ENOMEM); in rzv2h_cpg_pll_clk_register()
248 init.name = core->name; in rzv2h_cpg_pll_clk_register()
254 pll_clk->hw.init = &init; in rzv2h_cpg_pll_clk_register()
255 pll_clk->pll = core->cfg.pll; in rzv2h_cpg_pll_clk_register()
256 pll_clk->base = base; in rzv2h_cpg_pll_clk_register()
257 pll_clk->priv = priv; in rzv2h_cpg_pll_clk_register()
259 ret = devm_clk_hw_register(dev, &pll_clk->hw); in rzv2h_cpg_pll_clk_register()
263 return pll_clk->hw.clk; in rzv2h_cpg_pll_clk_register()
272 val = readl(divider->reg) >> divider->shift; in rzv2h_ddiv_recalc_rate()
273 val &= clk_div_mask(divider->width); in rzv2h_ddiv_recalc_rate()
275 return divider_recalc_rate(hw, parent_rate, val, divider->table, in rzv2h_ddiv_recalc_rate()
276 divider->flags, divider->width); in rzv2h_ddiv_recalc_rate()
284 return divider_round_rate(hw, rate, prate, divider->table, in rzv2h_ddiv_round_rate()
285 divider->width, divider->flags); in rzv2h_ddiv_round_rate()
293 return divider_determine_rate(hw, req, divider->table, divider->width, in rzv2h_ddiv_determine_rate()
294 divider->flags); in rzv2h_ddiv_determine_rate()
313 struct rzv2h_cpg_priv *priv = ddiv->priv; in rzv2h_ddiv_set_rate()
319 value = divider_get_val(rate, parent_rate, divider->table, in rzv2h_ddiv_set_rate()
320 divider->width, divider->flags); in rzv2h_ddiv_set_rate()
324 spin_lock_irqsave(divider->lock, flags); in rzv2h_ddiv_set_rate()
326 ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon); in rzv2h_ddiv_set_rate()
330 val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift); in rzv2h_ddiv_set_rate()
331 val &= ~(clk_div_mask(divider->width) << divider->shift); in rzv2h_ddiv_set_rate()
332 val |= (u32)value << divider->shift; in rzv2h_ddiv_set_rate()
333 writel(val, divider->reg); in rzv2h_ddiv_set_rate()
335 ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon); in rzv2h_ddiv_set_rate()
338 spin_unlock_irqrestore(divider->lock, flags); in rzv2h_ddiv_set_rate()
353 struct ddiv cfg_ddiv = core->cfg.ddiv; in rzv2h_cpg_ddiv_clk_register()
355 struct device *dev = priv->dev; in rzv2h_cpg_ddiv_clk_register()
364 parent = priv->clks[core->parent]; in rzv2h_cpg_ddiv_clk_register()
371 return ERR_PTR(-EINVAL); in rzv2h_cpg_ddiv_clk_register()
373 ddiv = devm_kzalloc(priv->dev, sizeof(*ddiv), GFP_KERNEL); in rzv2h_cpg_ddiv_clk_register()
375 return ERR_PTR(-ENOMEM); in rzv2h_cpg_ddiv_clk_register()
377 init.name = core->name; in rzv2h_cpg_ddiv_clk_register()
385 ddiv->priv = priv; in rzv2h_cpg_ddiv_clk_register()
386 ddiv->mon = cfg_ddiv.monbit; in rzv2h_cpg_ddiv_clk_register()
387 div = &ddiv->div; in rzv2h_cpg_ddiv_clk_register()
388 div->reg = priv->base + cfg_ddiv.offset; in rzv2h_cpg_ddiv_clk_register()
389 div->shift = shift; in rzv2h_cpg_ddiv_clk_register()
390 div->width = width; in rzv2h_cpg_ddiv_clk_register()
391 div->flags = core->flag; in rzv2h_cpg_ddiv_clk_register()
392 div->lock = &priv->rmw_lock; in rzv2h_cpg_ddiv_clk_register()
393 div->hw.init = &init; in rzv2h_cpg_ddiv_clk_register()
394 div->table = core->dtable; in rzv2h_cpg_ddiv_clk_register()
396 ret = devm_clk_hw_register(dev, &div->hw); in rzv2h_cpg_ddiv_clk_register()
400 return div->hw.clk; in rzv2h_cpg_ddiv_clk_register()
407 struct smuxed mux = core->cfg.smux; in rzv2h_cpg_mux_clk_register()
410 clk_hw = devm_clk_hw_register_mux(priv->dev, core->name, in rzv2h_cpg_mux_clk_register()
411 core->parent_names, core->num_parents, in rzv2h_cpg_mux_clk_register()
412 core->flag, priv->base + mux.offset, in rzv2h_cpg_mux_clk_register()
414 core->mux_flags, &priv->rmw_lock); in rzv2h_cpg_mux_clk_register()
418 return clk_hw->clk; in rzv2h_cpg_mux_clk_register()
425 unsigned int clkidx = clkspec->args[1]; in rzv2h_cpg_clk_src_twocell_get()
427 struct device *dev = priv->dev; in rzv2h_cpg_clk_src_twocell_get()
431 switch (clkspec->args[0]) { in rzv2h_cpg_clk_src_twocell_get()
434 if (clkidx > priv->last_dt_core_clk) { in rzv2h_cpg_clk_src_twocell_get()
436 return ERR_PTR(-EINVAL); in rzv2h_cpg_clk_src_twocell_get()
438 clk = priv->clks[clkidx]; in rzv2h_cpg_clk_src_twocell_get()
443 if (clkidx >= priv->num_mod_clks) { in rzv2h_cpg_clk_src_twocell_get()
445 return ERR_PTR(-EINVAL); in rzv2h_cpg_clk_src_twocell_get()
447 clk = priv->clks[priv->num_core_clks + clkidx]; in rzv2h_cpg_clk_src_twocell_get()
451 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); in rzv2h_cpg_clk_src_twocell_get()
452 return ERR_PTR(-EINVAL); in rzv2h_cpg_clk_src_twocell_get()
460 clkspec->args[0], clkspec->args[1], clk, in rzv2h_cpg_clk_src_twocell_get()
469 struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent; in rzv2h_cpg_register_core_clk()
470 unsigned int id = core->id, div = core->div; in rzv2h_cpg_register_core_clk()
471 struct device *dev = priv->dev; in rzv2h_cpg_register_core_clk()
475 WARN_DEBUG(id >= priv->num_core_clks); in rzv2h_cpg_register_core_clk()
476 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in rzv2h_cpg_register_core_clk()
478 switch (core->type) { in rzv2h_cpg_register_core_clk()
480 clk = of_clk_get_by_name(priv->dev->of_node, core->name); in rzv2h_cpg_register_core_clk()
483 WARN_DEBUG(core->parent >= priv->num_core_clks); in rzv2h_cpg_register_core_clk()
484 parent = priv->clks[core->parent]; in rzv2h_cpg_register_core_clk()
491 clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name, in rzv2h_cpg_register_core_clk()
493 core->mult, div); in rzv2h_cpg_register_core_clk()
497 clk = clk_hw->clk; in rzv2h_cpg_register_core_clk()
516 priv->clks[id] = clk; in rzv2h_cpg_register_core_clk()
521 core->name, PTR_ERR(clk)); in rzv2h_cpg_register_core_clk()
529 atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; in rzv2h_mod_clock_mstop_enable()
534 spin_lock_irqsave(&priv->rmw_lock, flags); in rzv2h_mod_clock_mstop_enable()
541 writel(val, priv->base + CPG_BUS_MSTOP(mstop_index)); in rzv2h_mod_clock_mstop_enable()
542 spin_unlock_irqrestore(&priv->rmw_lock, flags); in rzv2h_mod_clock_mstop_enable()
550 atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; in rzv2h_mod_clock_mstop_disable()
555 spin_lock_irqsave(&priv->rmw_lock, flags); in rzv2h_mod_clock_mstop_disable()
562 writel(val, priv->base + CPG_BUS_MSTOP(mstop_index)); in rzv2h_mod_clock_mstop_disable()
563 spin_unlock_irqrestore(&priv->rmw_lock, flags); in rzv2h_mod_clock_mstop_disable()
569 struct rzv2h_cpg_priv *priv = clock->priv; in rzv2h_mod_clock_is_enabled()
573 if (clock->mon_index >= 0) { in rzv2h_mod_clock_is_enabled()
574 offset = GET_CLK_MON_OFFSET(clock->mon_index); in rzv2h_mod_clock_is_enabled()
575 bitmask = BIT(clock->mon_bit); in rzv2h_mod_clock_is_enabled()
577 if (!(readl(priv->base + offset) & bitmask)) in rzv2h_mod_clock_is_enabled()
581 offset = GET_CLK_ON_OFFSET(clock->on_index); in rzv2h_mod_clock_is_enabled()
582 bitmask = BIT(clock->on_bit); in rzv2h_mod_clock_is_enabled()
584 return readl(priv->base + offset) & bitmask; in rzv2h_mod_clock_is_enabled()
591 unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index); in rzv2h_mod_clock_endisable()
592 struct rzv2h_cpg_priv *priv = clock->priv; in rzv2h_mod_clock_endisable()
593 u32 bitmask = BIT(clock->on_bit); in rzv2h_mod_clock_endisable()
594 struct device *dev = priv->dev; in rzv2h_mod_clock_endisable()
598 dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk, in rzv2h_mod_clock_endisable()
607 writel(value, priv->base + reg); in rzv2h_mod_clock_endisable()
608 if (clock->mstop_data != BUS_MSTOP_NONE) in rzv2h_mod_clock_endisable()
609 rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data); in rzv2h_mod_clock_endisable()
611 if (clock->mstop_data != BUS_MSTOP_NONE) in rzv2h_mod_clock_endisable()
612 rzv2h_mod_clock_mstop_disable(priv, clock->mstop_data); in rzv2h_mod_clock_endisable()
613 writel(value, priv->base + reg); in rzv2h_mod_clock_endisable()
616 if (!enable || clock->mon_index < 0) in rzv2h_mod_clock_endisable()
619 reg = GET_CLK_MON_OFFSET(clock->mon_index); in rzv2h_mod_clock_endisable()
620 bitmask = BIT(clock->mon_bit); in rzv2h_mod_clock_endisable()
621 error = readl_poll_timeout_atomic(priv->base + reg, value, in rzv2h_mod_clock_endisable()
625 GET_CLK_ON_OFFSET(clock->on_index), hw->clk); in rzv2h_mod_clock_endisable()
651 struct device *dev = priv->dev; in rzv2h_cpg_register_mod_clk()
658 id = GET_MOD_CLK_ID(priv->num_core_clks, mod->on_index, mod->on_bit); in rzv2h_cpg_register_mod_clk()
659 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); in rzv2h_cpg_register_mod_clk()
660 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); in rzv2h_cpg_register_mod_clk()
661 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in rzv2h_cpg_register_mod_clk()
663 parent = priv->clks[mod->parent]; in rzv2h_cpg_register_mod_clk()
671 clk = ERR_PTR(-ENOMEM); in rzv2h_cpg_register_mod_clk()
675 init.name = mod->name; in rzv2h_cpg_register_mod_clk()
678 if (mod->critical) in rzv2h_cpg_register_mod_clk()
685 clock->on_index = mod->on_index; in rzv2h_cpg_register_mod_clk()
686 clock->on_bit = mod->on_bit; in rzv2h_cpg_register_mod_clk()
687 clock->mon_index = mod->mon_index; in rzv2h_cpg_register_mod_clk()
688 clock->mon_bit = mod->mon_bit; in rzv2h_cpg_register_mod_clk()
689 clock->no_pm = mod->no_pm; in rzv2h_cpg_register_mod_clk()
690 clock->priv = priv; in rzv2h_cpg_register_mod_clk()
691 clock->hw.init = &init; in rzv2h_cpg_register_mod_clk()
692 clock->mstop_data = mod->mstop_data; in rzv2h_cpg_register_mod_clk()
694 ret = devm_clk_hw_register(dev, &clock->hw); in rzv2h_cpg_register_mod_clk()
700 priv->clks[id] = clock->hw.clk; in rzv2h_cpg_register_mod_clk()
707 if (clock->mstop_data != BUS_MSTOP_NONE && in rzv2h_cpg_register_mod_clk()
708 !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) { in rzv2h_cpg_register_mod_clk()
709 rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data); in rzv2h_cpg_register_mod_clk()
710 } else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) { in rzv2h_cpg_register_mod_clk()
711 unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data); in rzv2h_cpg_register_mod_clk()
712 u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data); in rzv2h_cpg_register_mod_clk()
713 atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; in rzv2h_cpg_register_mod_clk()
724 spin_lock_irqsave(&priv->rmw_lock, flags); in rzv2h_cpg_register_mod_clk()
732 writel(val, priv->base + CPG_BUS_MSTOP(mstop_index)); in rzv2h_cpg_register_mod_clk()
733 spin_unlock_irqrestore(&priv->rmw_lock, flags); in rzv2h_cpg_register_mod_clk()
740 mod->name, PTR_ERR(clk)); in rzv2h_cpg_register_mod_clk()
747 unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index); in __rzv2h_cpg_assert()
748 u32 mask = BIT(priv->resets[id].reset_bit); in __rzv2h_cpg_assert()
749 u8 monbit = priv->resets[id].mon_bit; in __rzv2h_cpg_assert()
752 dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n", in __rzv2h_cpg_assert()
757 writel(value, priv->base + reg); in __rzv2h_cpg_assert()
759 reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index); in __rzv2h_cpg_assert()
762 return readl_poll_timeout_atomic(priv->base + reg, value, in __rzv2h_cpg_assert()
795 unsigned int reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index); in rzv2h_cpg_status()
796 u8 monbit = priv->resets[id].mon_bit; in rzv2h_cpg_status()
798 return !!(readl(priv->base + reg) & BIT(monbit)); in rzv2h_cpg_status()
812 unsigned int id = reset_spec->args[0]; in rzv2h_cpg_reset_xlate()
817 for (i = 0; i < rcdev->nr_resets; i++) { in rzv2h_cpg_reset_xlate()
818 if (rst_index == priv->resets[i].reset_index && in rzv2h_cpg_reset_xlate()
819 rst_bit == priv->resets[i].reset_bit) in rzv2h_cpg_reset_xlate()
823 return -EINVAL; in rzv2h_cpg_reset_xlate()
828 priv->rcdev.ops = &rzv2h_cpg_reset_ops; in rzv2h_cpg_reset_controller_register()
829 priv->rcdev.of_node = priv->dev->of_node; in rzv2h_cpg_reset_controller_register()
830 priv->rcdev.dev = priv->dev; in rzv2h_cpg_reset_controller_register()
831 priv->rcdev.of_reset_n_cells = 1; in rzv2h_cpg_reset_controller_register()
832 priv->rcdev.of_xlate = rzv2h_cpg_reset_xlate; in rzv2h_cpg_reset_controller_register()
833 priv->rcdev.nr_resets = priv->num_resets; in rzv2h_cpg_reset_controller_register()
835 return devm_reset_controller_register(priv->dev, &priv->rcdev); in rzv2h_cpg_reset_controller_register()
839 * struct rzv2h_cpg_pd - RZ/V2H power domain data structure
840 * @priv: pointer to CPG private data structure
851 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) in rzv2h_cpg_is_pm_clk()
854 switch (clkspec->args[0]) { in rzv2h_cpg_is_pm_clk()
856 struct rzv2h_cpg_priv *priv = pd->priv; in rzv2h_cpg_is_pm_clk()
857 unsigned int id = clkspec->args[1]; in rzv2h_cpg_is_pm_clk()
860 if (id >= priv->num_mod_clks) in rzv2h_cpg_is_pm_clk()
863 if (priv->clks[priv->num_core_clks + id] == ERR_PTR(-ENOENT)) in rzv2h_cpg_is_pm_clk()
866 clock = to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id])); in rzv2h_cpg_is_pm_clk()
868 return !clock->no_pm; in rzv2h_cpg_is_pm_clk()
880 struct device_node *np = dev->of_node; in rzv2h_cpg_attach_dev()
887 for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) { in rzv2h_cpg_attach_dev()
940 struct device *dev = priv->dev; in rzv2h_cpg_add_pm_domains()
941 struct device_node *np = dev->of_node; in rzv2h_cpg_add_pm_domains()
947 return -ENOMEM; in rzv2h_cpg_add_pm_domains()
949 pd->genpd.name = np->name; in rzv2h_cpg_add_pm_domains()
950 pd->priv = priv; in rzv2h_cpg_add_pm_domains()
951 pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; in rzv2h_cpg_add_pm_domains()
952 pd->genpd.attach_dev = rzv2h_cpg_attach_dev; in rzv2h_cpg_add_pm_domains()
953 pd->genpd.detach_dev = rzv2h_cpg_detach_dev; in rzv2h_cpg_add_pm_domains()
954 ret = pm_genpd_init(&pd->genpd, &pm_domain_always_on_gov, false); in rzv2h_cpg_add_pm_domains()
958 ret = devm_add_action_or_reset(dev, rzv2h_cpg_genpd_remove_simple, &pd->genpd); in rzv2h_cpg_add_pm_domains()
962 return of_genpd_add_provider_simple(np, &pd->genpd); in rzv2h_cpg_add_pm_domains()
972 struct device *dev = &pdev->dev; in rzv2h_cpg_probe()
973 struct device_node *np = dev->of_node; in rzv2h_cpg_probe()
984 return -ENOMEM; in rzv2h_cpg_probe()
986 spin_lock_init(&priv->rmw_lock); in rzv2h_cpg_probe()
988 priv->dev = dev; in rzv2h_cpg_probe()
990 priv->base = devm_platform_ioremap_resource(pdev, 0); in rzv2h_cpg_probe()
991 if (IS_ERR(priv->base)) in rzv2h_cpg_probe()
992 return PTR_ERR(priv->base); in rzv2h_cpg_probe()
994 nclks = info->num_total_core_clks + info->num_hw_mod_clks; in rzv2h_cpg_probe()
997 return -ENOMEM; in rzv2h_cpg_probe()
999 priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits, in rzv2h_cpg_probe()
1000 sizeof(*priv->mstop_count), GFP_KERNEL); in rzv2h_cpg_probe()
1001 if (!priv->mstop_count) in rzv2h_cpg_probe()
1002 return -ENOMEM; in rzv2h_cpg_probe()
1005 priv->mstop_count -= 16; in rzv2h_cpg_probe()
1007 priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) * in rzv2h_cpg_probe()
1008 info->num_resets, GFP_KERNEL); in rzv2h_cpg_probe()
1009 if (!priv->resets) in rzv2h_cpg_probe()
1010 return -ENOMEM; in rzv2h_cpg_probe()
1013 priv->clks = clks; in rzv2h_cpg_probe()
1014 priv->num_core_clks = info->num_total_core_clks; in rzv2h_cpg_probe()
1015 priv->num_mod_clks = info->num_hw_mod_clks; in rzv2h_cpg_probe()
1016 priv->last_dt_core_clk = info->last_dt_core_clk; in rzv2h_cpg_probe()
1017 priv->num_resets = info->num_resets; in rzv2h_cpg_probe()
1020 clks[i] = ERR_PTR(-ENOENT); in rzv2h_cpg_probe()
1022 for (i = 0; i < info->num_core_clks; i++) in rzv2h_cpg_probe()
1023 rzv2h_cpg_register_core_clk(&info->core_clks[i], priv); in rzv2h_cpg_probe()
1025 for (i = 0; i < info->num_mod_clks; i++) in rzv2h_cpg_probe()
1026 rzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv); in rzv2h_cpg_probe()
1050 .compatible = "renesas,r9a09g047-cpg",
1056 .compatible = "renesas,r9a09g056-cpg",
1062 .compatible = "renesas,r9a09g057-cpg",
1071 .name = "rzv2h-cpg",
1083 MODULE_DESCRIPTION("Renesas RZ/V2H CPG Driver");