Lines Matching refs:mux_dsi_div_params
152 * @mux_dsi_div_params: pll5 mux and dsi div parameters
170 struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
612 if (priv->mux_dsi_div_params.clksrc)
649 (priv->mux_dsi_div_params.dsi_div_a << 0) |
650 (priv->mux_dsi_div_params.dsi_div_b << 8),
716 parent = clk_hw_get_parent_by_index(hw, priv->mux_dsi_div_params.clksrc);
806 vclk = rate / ((1 << priv->mux_dsi_div_params.dsi_div_a) *
807 (priv->mux_dsi_div_params.dsi_div_b + 1));
809 if (priv->mux_dsi_div_params.clksrc)
949 priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */
950 priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */
951 priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */