Lines Matching defs:clk_hw_data
78 * struct clk_hw_data - clock hardware data
84 struct clk_hw_data {
91 #define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw)
99 struct clk_hw_data hw_data;
114 struct clk_hw_data hw_data;
193 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
194 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
195 u32 off = GET_REG_OFFSET(clk_hw_data->conf);
196 u32 shift = GET_SHIFT(clk_hw_data->conf);
221 ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
236 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
237 struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data);
238 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
239 u32 off = GET_REG_OFFSET(clk_hw_data->conf);
240 u32 shift = GET_SHIFT(clk_hw_data->conf);
253 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);
267 ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
298 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
299 struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data);
300 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
303 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf));
304 val >>= GET_SHIFT(clk_hw_data->conf);
305 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);
313 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
314 struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data);
326 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
327 struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data);
328 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
329 u32 off = GET_REG_OFFSET(clk_hw_data->conf);
330 u32 shift = GET_SHIFT(clk_hw_data->conf);
341 ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
472 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
473 struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data);
474 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
475 u32 off = GET_REG_OFFSET(clk_hw_data->conf);
476 u32 shift = GET_SHIFT(clk_hw_data->conf);
488 ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
500 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
501 struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data);
502 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
505 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf));
506 val >>= GET_SHIFT(clk_hw_data->conf);
507 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);
666 struct dsi_div_hw_data *clk_hw_data;
677 clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
678 if (!clk_hw_data)
681 clk_hw_data->priv = priv;
690 clk_hw = &clk_hw_data->hw;
762 struct pll5_mux_hw_data *clk_hw_data;
767 clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
768 if (!clk_hw_data)
771 clk_hw_data->priv = priv;
772 clk_hw_data->conf = core->conf;
780 clk_hw = &clk_hw_data->hw;