Lines Matching +full:- +full:cpg +full:- +full:mssr

1 /* SPDX-License-Identifier: GPL-2.0 */
14      * Definitions of CPG Core Clocks
17      *   - Clock outputs exported to DT
18      *   - External input clocks
19      *   - Internal CPG clocks
43  * struct cpg_mssr_pub - data shared with device-specific clk registration code
45  * @base0: CPG/MSSR register block base0 address
46  * @base1: CPG/MSSR register block base1 address
97 /* Convert from sparse base-100 to packed index space */
98 #define MOD_CLK_PACK(x)	((x) - ((x) / 100) * (100 - 32))
105 /* Convert from sparse base-10 to packed index space */
123      * SoC-specific CPG/MSSR Description
142      * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
148      * @init: Optional callback to perform SoC-specific initialization