Lines Matching +full:cpg +full:- +full:mstp +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "renesas-cpg-mssr.h"
35 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
48 * These are NOT valid for R-Car Gen1 and RZ/A1!
157 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
162 * @dev: CPG/MSSR device
163 * @reg_layout: CPG/MSSR register layout
164 * @np: Device node in DT for this CPG/MSSR module
165 * @num_core_clks: Number of Core Clocks in clks[]
166 * @num_mod_clks: Number of Module Clocks in clks[]
176 * @clks: Array containing all Core and Module Clocks
209 * struct mstp_clock - MSTP gating clock
210 * @hw: handle between common and hardware-specific interfaces
211 * @index: MSTP clock number
212 * @priv: CPG/MSSR private data
225 struct cpg_mssr_priv *priv = clock->priv; in cpg_rzt2h_mstp_read()
227 RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0; in cpg_rzt2h_mstp_read()
235 struct cpg_mssr_priv *priv = clock->priv; in cpg_rzt2h_mstp_write()
237 RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0; in cpg_rzt2h_mstp_write()
245 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_endisable()
246 unsigned int reg = clock->index / 32; in cpg_mstp_clock_endisable()
247 unsigned int bit = clock->index % 32; in cpg_mstp_clock_endisable()
248 struct device *dev = priv->dev; in cpg_mstp_clock_endisable()
254 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, in cpg_mstp_clock_endisable()
256 spin_lock_irqsave(&priv->pub.rmw_lock, flags); in cpg_mstp_clock_endisable()
258 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
259 value = readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
264 writeb(value, priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
267 readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
268 barrier_data(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
270 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mstp_clock_endisable()
272 priv->control_regs[reg]); in cpg_mstp_clock_endisable()
280 priv->control_regs[reg], in cpg_mstp_clock_endisable()
283 value = readl(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
288 writel(value, priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
291 spin_unlock_irqrestore(&priv->pub.rmw_lock, flags); in cpg_mstp_clock_endisable()
293 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A || in cpg_mstp_clock_endisable()
294 priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) in cpg_mstp_clock_endisable()
297 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], in cpg_mstp_clock_endisable()
301 priv->pub.base0 + priv->control_regs[reg], bit); in cpg_mstp_clock_endisable()
319 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_is_enabled()
320 unsigned int reg = clock->index / 32; in cpg_mstp_clock_is_enabled()
323 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
324 value = readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_is_enabled()
325 else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) in cpg_mstp_clock_is_enabled()
327 priv->control_regs[reg]); in cpg_mstp_clock_is_enabled()
329 value = readl(priv->pub.base0 + priv->status_regs[reg]); in cpg_mstp_clock_is_enabled()
331 return !(value & BIT(clock->index % 32)); in cpg_mstp_clock_is_enabled()
344 unsigned int clkidx = clkspec->args[1]; in cpg_mssr_clk_src_twocell_get()
346 struct device *dev = priv->dev; in cpg_mssr_clk_src_twocell_get()
352 switch (clkspec->args[0]) { in cpg_mssr_clk_src_twocell_get()
355 if (clkidx > priv->last_dt_core_clk) { in cpg_mssr_clk_src_twocell_get()
358 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
360 clk = priv->clks[clkidx]; in cpg_mssr_clk_src_twocell_get()
365 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
367 range_check = 7 - (clkidx % 10); in cpg_mssr_clk_src_twocell_get()
370 range_check = 31 - (clkidx % 100); in cpg_mssr_clk_src_twocell_get()
372 if (range_check < 0 || idx >= priv->num_mod_clks) { in cpg_mssr_clk_src_twocell_get()
375 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
377 clk = priv->clks[priv->num_core_clks + idx]; in cpg_mssr_clk_src_twocell_get()
381 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); in cpg_mssr_clk_src_twocell_get()
382 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
390 clkspec->args[0], clkspec->args[1], clk, in cpg_mssr_clk_src_twocell_get()
399 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; in cpg_mssr_register_core_clk()
400 struct device *dev = priv->dev; in cpg_mssr_register_core_clk()
401 unsigned int id = core->id, div = core->div; in cpg_mssr_register_core_clk()
404 WARN_DEBUG(id >= priv->num_core_clks); in cpg_mssr_register_core_clk()
405 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in cpg_mssr_register_core_clk()
407 switch (core->type) { in cpg_mssr_register_core_clk()
409 clk = of_clk_get_by_name(priv->np, core->name); in cpg_mssr_register_core_clk()
415 WARN_DEBUG(core->parent >= priv->num_core_clks); in cpg_mssr_register_core_clk()
416 parent = priv->pub.clks[core->parent]; in cpg_mssr_register_core_clk()
424 if (core->type == CLK_TYPE_DIV6_RO) in cpg_mssr_register_core_clk()
426 div *= (readl(priv->pub.base0 + core->offset) & 0x3f) + 1; in cpg_mssr_register_core_clk()
428 if (core->type == CLK_TYPE_DIV6P1) { in cpg_mssr_register_core_clk()
429 clk = cpg_div6_register(core->name, 1, &parent_name, in cpg_mssr_register_core_clk()
430 priv->pub.base0 + core->offset, in cpg_mssr_register_core_clk()
431 &priv->pub.notifiers); in cpg_mssr_register_core_clk()
433 clk = clk_register_fixed_factor(NULL, core->name, in cpg_mssr_register_core_clk()
435 core->mult, div); in cpg_mssr_register_core_clk()
440 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, in cpg_mssr_register_core_clk()
441 core->mult); in cpg_mssr_register_core_clk()
445 if (info->cpg_clk_register) in cpg_mssr_register_core_clk()
446 clk = info->cpg_clk_register(dev, core, info, in cpg_mssr_register_core_clk()
447 &priv->pub); in cpg_mssr_register_core_clk()
450 core->name, core->type); in cpg_mssr_register_core_clk()
458 priv->pub.clks[id] = clk; in cpg_mssr_register_core_clk()
463 core->name, PTR_ERR(clk)); in cpg_mssr_register_core_clk()
471 struct device *dev = priv->dev; in cpg_mssr_register_mod_clk()
472 unsigned int id = mod->id; in cpg_mssr_register_mod_clk()
478 WARN_DEBUG(id < priv->num_core_clks); in cpg_mssr_register_mod_clk()
479 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
480 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
481 WARN_DEBUG(PTR_ERR(priv->pub.clks[id]) != -ENOENT); in cpg_mssr_register_mod_clk()
483 if (!mod->name) { in cpg_mssr_register_mod_clk()
488 parent = priv->pub.clks[mod->parent]; in cpg_mssr_register_mod_clk()
496 clk = ERR_PTR(-ENOMEM); in cpg_mssr_register_mod_clk()
500 init.name = mod->name; in cpg_mssr_register_mod_clk()
507 clock->index = id - priv->num_core_clks; in cpg_mssr_register_mod_clk()
508 clock->priv = priv; in cpg_mssr_register_mod_clk()
509 clock->hw.init = &init; in cpg_mssr_register_mod_clk()
511 for (i = 0; i < info->num_crit_mod_clks; i++) in cpg_mssr_register_mod_clk()
512 if (id == info->crit_mod_clks[i] && in cpg_mssr_register_mod_clk()
513 cpg_mstp_clock_is_enabled(&clock->hw)) { in cpg_mssr_register_mod_clk()
514 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", in cpg_mssr_register_mod_clk()
515 mod->name); in cpg_mssr_register_mod_clk()
525 for (i = 0; i < priv->num_reserved_ids; i++) { in cpg_mssr_register_mod_clk()
526 if (id == priv->reserved_ids[i]) { in cpg_mssr_register_mod_clk()
527 dev_info(dev, "Ignore Linux non-assigned mod (%s)\n", mod->name); in cpg_mssr_register_mod_clk()
533 clk = clk_register(NULL, &clock->hw); in cpg_mssr_register_mod_clk()
538 priv->clks[id] = clk; in cpg_mssr_register_mod_clk()
539 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); in cpg_mssr_register_mod_clk()
544 mod->name, PTR_ERR(clk)); in cpg_mssr_register_mod_clk()
561 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) in cpg_mssr_is_pm_clk()
564 switch (clkspec->args[0]) { in cpg_mssr_is_pm_clk()
566 for (i = 0; i < pd->num_core_pm_clks; i++) in cpg_mssr_is_pm_clk()
567 if (clkspec->args[1] == pd->core_pm_clks[i]) in cpg_mssr_is_pm_clk()
582 struct device_node *np = dev->of_node; in cpg_mssr_attach_dev()
589 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); in cpg_mssr_attach_dev()
590 return -EPROBE_DEFER; in cpg_mssr_attach_dev()
593 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, in cpg_mssr_attach_dev()
643 struct device_node *np = dev->of_node; in cpg_mssr_add_clk_domain()
651 return -ENOMEM; in cpg_mssr_add_clk_domain()
653 pd->num_core_pm_clks = num_core_pm_clks; in cpg_mssr_add_clk_domain()
654 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); in cpg_mssr_add_clk_domain()
656 genpd = &pd->genpd; in cpg_mssr_add_clk_domain()
657 genpd->name = np->name; in cpg_mssr_add_clk_domain()
658 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | in cpg_mssr_add_clk_domain()
660 genpd->attach_dev = cpg_mssr_attach_dev; in cpg_mssr_add_clk_domain()
661 genpd->detach_dev = cpg_mssr_detach_dev; in cpg_mssr_add_clk_domain()
687 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); in cpg_mssr_reset()
690 writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]); in cpg_mssr_reset()
696 writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]); in cpg_mssr_reset()
708 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); in cpg_mssr_assert()
710 writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]); in cpg_mssr_assert()
722 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); in cpg_mssr_deassert()
724 writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]); in cpg_mssr_deassert()
736 return !!(readl(priv->pub.base0 + priv->reset_regs[reg]) & bitmask); in cpg_mssr_status()
750 unsigned int unpacked = reset_spec->args[0]; in cpg_mssr_reset_xlate()
753 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { in cpg_mssr_reset_xlate()
754 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); in cpg_mssr_reset_xlate()
755 return -EINVAL; in cpg_mssr_reset_xlate()
763 priv->rcdev.ops = &cpg_mssr_reset_ops; in cpg_mssr_reset_controller_register()
764 priv->rcdev.of_node = priv->dev->of_node; in cpg_mssr_reset_controller_register()
765 priv->rcdev.of_reset_n_cells = 1; in cpg_mssr_reset_controller_register()
766 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; in cpg_mssr_reset_controller_register()
767 priv->rcdev.nr_resets = priv->num_mod_clks; in cpg_mssr_reset_controller_register()
768 return devm_reset_controller_register(priv->dev, &priv->rcdev); in cpg_mssr_reset_controller_register()
781 .compatible = "renesas,r7s9210-cpg-mssr",
787 .compatible = "renesas,r8a7742-cpg-mssr",
793 .compatible = "renesas,r8a7743-cpg-mssr",
796 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
798 .compatible = "renesas,r8a7744-cpg-mssr",
804 .compatible = "renesas,r8a7745-cpg-mssr",
810 .compatible = "renesas,r8a77470-cpg-mssr",
816 .compatible = "renesas,r8a774a1-cpg-mssr",
822 .compatible = "renesas,r8a774b1-cpg-mssr",
828 .compatible = "renesas,r8a774c0-cpg-mssr",
834 .compatible = "renesas,r8a774e1-cpg-mssr",
840 .compatible = "renesas,r8a7790-cpg-mssr",
846 .compatible = "renesas,r8a7791-cpg-mssr",
849 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
851 .compatible = "renesas,r8a7793-cpg-mssr",
857 .compatible = "renesas,r8a7792-cpg-mssr",
863 .compatible = "renesas,r8a7794-cpg-mssr",
869 .compatible = "renesas,r8a7795-cpg-mssr",
875 .compatible = "renesas,r8a7796-cpg-mssr",
881 .compatible = "renesas,r8a77961-cpg-mssr",
887 .compatible = "renesas,r8a77965-cpg-mssr",
893 .compatible = "renesas,r8a77970-cpg-mssr",
899 .compatible = "renesas,r8a77980-cpg-mssr",
905 .compatible = "renesas,r8a77990-cpg-mssr",
911 .compatible = "renesas,r8a77995-cpg-mssr",
917 .compatible = "renesas,r8a779a0-cpg-mssr",
923 .compatible = "renesas,r8a779f0-cpg-mssr",
929 .compatible = "renesas,r8a779g0-cpg-mssr",
935 .compatible = "renesas,r8a779h0-cpg-mssr",
941 .compatible = "renesas,r9a09g077-cpg-mssr",
947 .compatible = "renesas,r9a09g087-cpg-mssr",
970 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_suspend_noirq()
971 if (priv->smstpcr_saved[reg].mask) in cpg_mssr_suspend_noirq()
972 priv->smstpcr_saved[reg].val = in cpg_mssr_suspend_noirq()
973 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
974 readb(priv->pub.base0 + priv->control_regs[reg]) : in cpg_mssr_suspend_noirq()
975 readl(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_suspend_noirq()
978 /* Save core clocks */ in cpg_mssr_suspend_noirq()
979 raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_SUSPEND, NULL); in cpg_mssr_suspend_noirq()
995 /* Restore core clocks */ in cpg_mssr_resume_noirq()
996 raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_RESUME, NULL); in cpg_mssr_resume_noirq()
998 /* Restore module clocks */ in cpg_mssr_resume_noirq()
999 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_resume_noirq()
1000 mask = priv->smstpcr_saved[reg].mask; in cpg_mssr_resume_noirq()
1004 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
1005 oldval = readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1007 oldval = readl(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1009 newval |= priv->smstpcr_saved[reg].val & mask; in cpg_mssr_resume_noirq()
1013 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq()
1014 writeb(newval, priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1016 readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1017 barrier_data(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1020 writel(newval, priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1022 /* Wait until enabled clocks are really enabled */ in cpg_mssr_resume_noirq()
1023 mask &= ~priv->smstpcr_saved[reg].val; in cpg_mssr_resume_noirq()
1027 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], in cpg_mssr_resume_noirq()
1048 kfree(priv->reserved_ids); in cpg_mssr_reserved_exit()
1061 * Because clk_disable_unused() will disable all unused clocks, the device which is assigned in cpg_mssr_reserved_init()
1062 * to a non-Linux system will be disabled when Linux is booted. in cpg_mssr_reserved_init()
1064 * To avoid such situation, renesas-cpg-mssr assumes the device which has in cpg_mssr_reserved_init()
1065 * status = "reserved" is assigned to a non-Linux system, and adds CLK_IGNORE_UNUSED flag in cpg_mssr_reserved_init()
1066 * to its CPG_MOD clocks. in cpg_mssr_reserved_init()
1072 * => clocks = <&cpg CPG_MOD 202>, in cpg_mssr_reserved_init()
1073 * <&cpg CPG_CORE R8A7795_CLK_S3D1>, in cpg_mssr_reserved_init()
1083 of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) { in cpg_mssr_reserved_init()
1087 if (it.node != priv->np) in cpg_mssr_reserved_init()
1100 return -ENOMEM; in cpg_mssr_reserved_init()
1104 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_reserved_init()
1109 ids[num] = info->num_total_core_clks + idx; in cpg_mssr_reserved_init()
1115 priv->num_reserved_ids = num; in cpg_mssr_reserved_init()
1116 priv->reserved_ids = ids; in cpg_mssr_reserved_init()
1129 if (info->init) { in cpg_mssr_common_init()
1130 error = info->init(dev); in cpg_mssr_common_init()
1135 nclks = info->num_total_core_clks + info->num_hw_mod_clks; in cpg_mssr_common_init()
1138 return -ENOMEM; in cpg_mssr_common_init()
1140 priv->pub.clks = priv->clks; in cpg_mssr_common_init()
1141 priv->np = np; in cpg_mssr_common_init()
1142 priv->dev = dev; in cpg_mssr_common_init()
1143 spin_lock_init(&priv->pub.rmw_lock); in cpg_mssr_common_init()
1145 priv->pub.base0 = of_iomap(np, 0); in cpg_mssr_common_init()
1146 if (!priv->pub.base0) { in cpg_mssr_common_init()
1147 error = -ENOMEM; in cpg_mssr_common_init()
1150 if (info->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mssr_common_init()
1151 priv->pub.base1 = of_iomap(np, 1); in cpg_mssr_common_init()
1152 if (!priv->pub.base1) { in cpg_mssr_common_init()
1153 error = -ENOMEM; in cpg_mssr_common_init()
1158 priv->num_core_clks = info->num_total_core_clks; in cpg_mssr_common_init()
1159 priv->num_mod_clks = info->num_hw_mod_clks; in cpg_mssr_common_init()
1160 priv->last_dt_core_clk = info->last_dt_core_clk; in cpg_mssr_common_init()
1161 RAW_INIT_NOTIFIER_HEAD(&priv->pub.notifiers); in cpg_mssr_common_init()
1162 priv->reg_layout = info->reg_layout; in cpg_mssr_common_init()
1163 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { in cpg_mssr_common_init()
1164 priv->status_regs = mstpsr; in cpg_mssr_common_init()
1165 priv->control_regs = smstpcr; in cpg_mssr_common_init()
1166 priv->reset_regs = srcr; in cpg_mssr_common_init()
1167 priv->reset_clear_regs = srstclr; in cpg_mssr_common_init()
1168 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_common_init()
1169 priv->control_regs = stbcr; in cpg_mssr_common_init()
1170 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mssr_common_init()
1171 priv->control_regs = mstpcr_for_rzt2h; in cpg_mssr_common_init()
1172 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { in cpg_mssr_common_init()
1173 priv->status_regs = mstpsr_for_gen4; in cpg_mssr_common_init()
1174 priv->control_regs = mstpcr_for_gen4; in cpg_mssr_common_init()
1175 priv->reset_regs = srcr_for_gen4; in cpg_mssr_common_init()
1176 priv->reset_clear_regs = srstclr_for_gen4; in cpg_mssr_common_init()
1178 error = -EINVAL; in cpg_mssr_common_init()
1183 priv->pub.clks[i] = ERR_PTR(-ENOENT); in cpg_mssr_common_init()
1200 if (priv->pub.base0) in cpg_mssr_common_init()
1201 iounmap(priv->pub.base0); in cpg_mssr_common_init()
1202 if (priv->pub.base1) in cpg_mssr_common_init()
1203 iounmap(priv->pub.base1); in cpg_mssr_common_init()
1219 for (i = 0; i < info->num_early_core_clks; i++) in cpg_mssr_early_init()
1220 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, in cpg_mssr_early_init()
1223 for (i = 0; i < info->num_early_mod_clks; i++) in cpg_mssr_early_init()
1224 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, in cpg_mssr_early_init()
1231 struct device *dev = &pdev->dev; in cpg_mssr_probe()
1232 struct device_node *np = dev->of_node; in cpg_mssr_probe()
1241 error = cpg_mssr_common_init(dev, dev->of_node, info); in cpg_mssr_probe()
1247 priv->dev = dev; in cpg_mssr_probe()
1250 for (i = 0; i < info->num_core_clks; i++) in cpg_mssr_probe()
1251 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); in cpg_mssr_probe()
1253 for (i = 0; i < info->num_mod_clks; i++) in cpg_mssr_probe()
1254 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); in cpg_mssr_probe()
1262 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, in cpg_mssr_probe()
1263 info->num_core_pm_clks); in cpg_mssr_probe()
1268 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A || in cpg_mssr_probe()
1269 priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) in cpg_mssr_probe()
1282 .name = "renesas-cpg-mssr",
1308 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");